A design-for-test structure for optimising analogue and mixed signal IC test

Abstract

A new Design-for-Test (DjT) structure based on a configurable operational amplijier, referred to as a "swap amp" is presented that allows access to embedded analogue blocks. The structure has minimal impact on circuit performance and has been evaluated on a custom designed Phase Locked Loop (PLL) structure. A test chip containing faulty and fault free versions of this PLL structure, with and without DjT modifications, has been fabricated and an evaluation of this DjT scheme based on the swap-amp structure carried out. It is shown that for embedded analogue blocks, the DjT strategy can not only improve and simplify analogue & mixed signal IC test, but can also be used for diagnostics.simple to implement and the problem of backdriving is totally eliminated. Application of the D f f scheme to a phase-locked-loop circuit is presented. The scheme is shown to greatly improve both detection and diagnostic capabilities associated with a number of hard and soft faults. The format of the paper will be as follows; Section 2 will identify related work, sections 3 and 4 will then discuss critical issues in the design of an analogue Dff architecture and identifies the optimal placement of switches. Section 5 will describe the design of the swapamp and present an analysis of its performance. In section 6, a Dff scheme exploiting the "swap-amp'' design is discussed and in section 7 the test chip fabricated to access the fault detection and diagnostic capabilities of the scheme is described. Section 8 will present results from the silicon and section 9 will conclude and discuss future work.

Fault-based testing and diagnosis of balanced filters

“…This approach is extended in [8] to cope with switched-capacitor (SC) circuits. A DFr scheme which modifies operational amplifiers to include a test mode is presented in [9]. The test mode allows the isolation of analogue blocks and provides access to them without an important degradation of circuit performance.…”

A digital partial built-in self-test structure for a high performance automatic gain control circuit

“…The Analogue Circuit Observer Block [19] reduces the need for precision by encoding the data during circuit test. A DfT system level architecture, using the sw-opamp concept [20], improves the controllability and observability in a multi stage circuit and includes off-and on-line tests with BIST capabilities [14]. A similar demonstrator has been chosen for AUBIST [21] which compares the output response of cascaded biquads.…”

A design for testability study on a high performance automatic gain control circuit

“…This test can be run in parallel with the stand-by mode test for faults in OP1, as its output can be driven to VDD or VSS. Future work will examine the use of the swopamp design 13,19 as the structure of OP1 and OP2 is compatible with this approach. …”

“…The Analogue Circuit Observer Block 18 reduces the need for precision by encoding the data during circuit test. A DfT system level architecture, using the sw-opamp concept 19 , improves the controllability and observability in a multi stage circuit and includes off-and on-line tests with BIST capabilities 13 . A similar demonstrator has been chosen for AUBIST 20,21 which compares the output response of cascaded biquads.…”