A. Brat$ 2. University 1. Motorola SPS -Logic and h a l o Technolo ies Group, Tempe, AZ 85284, of Arizona ECE Dept. Tuscon, AZ 8 5 7 2 1 , 3 .~i n g t o n~i c r~e l e c t r o n i c s Limited, Northwich, Cheshire, UK. AbstractA Field Programmable Analog Array (FPAA) is presented based on switched capacitor technology. The architecture offers an unconstrained topology similar to its digital counterpart, containing an array of identical undedicated analog cells. This makes it possible to program both the functionality of each cell and the interconnect between cells. As a result a large number of diverse architectures may be implemented.The analog array can be programmed to perform many of the routine tasks associated with control systems design. It's linear and non-linear signal processing abilities can provide a wide range of waveform generation functions. The device can also be programmed for precise phase and magnitude characteristics. Some examples related to control systems are discussed.

A new Design-for-Test (DjT) structure based on a configurable operational amplijier, referred to as a "swap amp" is presented that allows access to embedded analogue blocks. The structure has minimal impact on circuit performance and has been evaluated on a custom designed Phase Locked Loop (PLL) structure. A test chip containing faulty and fault free versions of this PLL structure, with and without DjT modifications, has been fabricated and an evaluation of this DjT scheme based on the swap-amp structure carried out. It is shown that for embedded analogue blocks, the DjT strategy can not only improve and simplify analogue & mixed signal IC test, but can also be used for diagnostics.simple to implement and the problem of backdriving is totally eliminated. Application of the D f f scheme to a phase-locked-loop circuit is presented. The scheme is shown to greatly improve both detection and diagnostic capabilities associated with a number of hard and soft faults. The format of the paper will be as follows; Section 2 will identify related work, sections 3 and 4 will then discuss critical issues in the design of an analogue Dff architecture and identifies the optimal placement of switches. Section 5 will describe the design of the swapamp and present an analysis of its performance. In section 6, a Dff scheme exploiting the "swap-amp'' design is discussed and in section 7 the test chip fabricated to access the fault detection and diagnostic capabilities of the scheme is described. Section 8 will present results from the silicon and section 9 will conclude and discuss future work.

No abstract

No abstract

No abstract