On the development of power supply voltage control testing technique for analogue circuits

A'ain, A.K.B.; Bratt, A.H.; Dorey, A.P.

doi:10.1109/ats.1995.485328

Cited by 9 publications

(7 citation statements)

References 6 publications

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“…a) A square-wave or pulse is chosen due to its transient characteristic. In [11], AC/transient test is required to obtain higher fault coverage for analogue circuit and, it is easy to generate from industry power supply instrument and digital tester. Besides, it can be directly implemented to the digital circuit.…”

Section: Digital Modelling Test Techniquementioning

confidence: 99%

“…Power Supply Control test technique [11] was also coupled with digital Model technique to test the CUT. This is due to high fault coverage that had been achieved using power supply voltage control approach on digital and analogue circuits.…”

Section: Power Supply Voltage Control Test Techniquementioning

confidence: 99%

“…This is due to high fault coverage that had been achieved using power supply voltage control approach on digital and analogue circuits. It was found in [11] that the effect of defects has better change to propagate in the CUT to its primary output which resulted them to be exposed by analysing the sequence of bias point analysis.…”

Section: Power Supply Voltage Control Test Techniquementioning

confidence: 99%

“…This to cause variation in V DS and V GS as reported in [11]. For this investigation, CUT was configured and simulated like the setting in Table 1.…”

Section: Power Supply Voltage Control Test Techniquementioning

confidence: 99%

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An investigation on ADC testing using digital modelling

Hon

A’ain

2004

2004 IEEE Region 10 Conference TENCON 2004.

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This paper presents an analysis of test results of digital model approach on Analogue-to-digital converter (ADC). The approach is to inject primary input with arbitrary frequencies and periodical digital pulse. The output response is sampled and analysed in order to distinguish between GO or No-GO. Furthermore, the proposed technique is also coupled with power supply voltage control test technique to investigate the fault coverage margin. Histogram test, conventional industrial test technique, simulates concurrently were also employed as a comparison study.

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Section: Digital Modelling Test Techniquementioning

confidence: 99%

Section: Power Supply Voltage Control Test Techniquementioning

confidence: 99%

Section: Power Supply Voltage Control Test Techniquementioning

confidence: 99%

“…This to cause variation in V DS and V GS as reported in [11]. For this investigation, CUT was configured and simulated like the setting in Table 1.…”

Section: Power Supply Voltage Control Test Techniquementioning

confidence: 99%

See 2 more Smart Citations

An investigation on ADC testing using digital modelling

Hon

A’ain

2004

2004 IEEE Region 10 Conference TENCON 2004.

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“…To avoid the second problem, a power supply voltage control technique to degrade the ATE-provided power integrity is required. However, existing power supply voltage control techniques that would inject noise into the power supply [1,2,15] or lower the power supply voltage [5] intend to detect additional defects. Therefore, these methods cannot emulate the power supply noise that is occurred in typical operating environments, underkills may not be sufficiently removed and may induce more overkills.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

et al. 2016

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This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feedforward manner such that the ATE power supply waveform matches with the one on the customer's operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer's operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.

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A BIST-DFT technique for DC test of analog modules

Dufaza

Ihs

1996

J Electron Test

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Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-In Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults.

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On the development of power supply voltage control testing technique for analogue circuits

Cited by 9 publications

References 6 publications

An investigation on ADC testing using digital modelling

An investigation on ADC testing using digital modelling

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

A BIST-DFT technique for DC test of analog modules

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