A BIST-DFT technique for DC test of analog modules

Dufaza, C.; Ihs, H.

doi:10.1007/bf00137569

Cited by 11 publications

(7 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These voltage-based techniques have been realized extensively in most cost-effective BIST systems [9][10], as faults can be detected instantaneously and effectively, yielding low area overhead, especially in LSI or ASIC applications. However, effective sampling methods of specific input test stimuli types are difficult to achieve due to complexities such as the realization of a phase-locked or delay-locked loops [11].…”

Section: Introductionmentioning

confidence: 99%

Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits

San-Um

Tachibana

2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

View full text Add to dashboard Cite

This paper proposes a new impulse stimulation and response sampling technique for the implementation of a Built-In Self Test of linear analog integrated circuits embedded in mixed-signal systems. The testing technique is the monitoring of physical fault influences on impulse response characteristics through the use of single-point sampling method and window criterions. The implementation of BIST system realizes a controllable impulse generator, which provide two short impulses simultaneously for stimulating a Circuit-Under-Test, and sampling a transient impulse response. This proposed technique is cost-effective and relatively compact. Neither high-precision analog test stimuli with fault-free bit streams nor characterization and synchronization processes in DSP are required. Demonstrations of the BIST system for a Sallen-Key low-pass filter in a physical level using 0.18-µm CMOS technology show a low area overhead of 11.19%, and offer high catastrophic and parameter fault coverage of 98.24%.

show abstract

Section: Introductionmentioning

confidence: 99%

Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits

San-Um

Tachibana

2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

View full text Add to dashboard Cite

show abstract

“…First, one should select an analog test domain [1]. Testing can be done by analyzing DC signals [2,3,4], signals in the frequency domain [5,6,7], as well as the signals in the time domain [8]. It is often necessary to use test signals from several domains simultaneously.…”

Section: Introductionmentioning

confidence: 99%

Oscillation-based testing method for detecting switch faults in High-Q SC biquad filters

Milic

Litovski

2015

FACTA U EE

View full text Add to dashboard Cite

Testing switched capacitor circuits is a challenge due to the diversity of the possible faults. A special problem encountered is the synthesis of the test signal that will control and make the fault-effect observable at the test point. The oscillation based method which was adopted for testing in these proceedings resolves that important issue in its nature. Here we discuss the properties of the method and the conditions to be fulfilled in order to implement it in the right way. To achieve that, we have resolved the problem of synthesis of the positive feedback circuit and the choice of a proper model of the operational amplifier. In that way, a realistic foundation to the testing process was generated. A second order notch cell was chosen as a case-study. Fault dictionaries were developed related to the catastrophic faults of the switches used within the cell. The results reported here are a continuation of our previous work and are complimentary to some other already published.

show abstract

“…However, a circuit-undertest (CUT) may suffer from power supply variations, and inappropriate setting of reference currents may also affect the precision of fault detection owing to a wide range of faulty currents [5]. On the other hand, the voltage sensing techniques include two main categories; the DC voltage sensing such as the built-in voltage sensor [6] and the V DDQ scheme [7], and the AC output response characterizations such as sub-sampling [8], absolute value difference [9], on-chip spectrum analyzer [10], and ΣΔ modulator [11]. These voltage-sensing techniques support non-intrusive implementation, and offer suitability for most types of circuits as only output signals are monitored with no modification in CUTs.…”

Section: Introductionmentioning

confidence: 99%

A Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard

San-Um¹,

Tachibana²

2010

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

A Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 StandardWimol SAN-UM †a) , Nonmember and Masayoshi TACHIBANA †b) , Member SUMMARY An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-μm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides nonintrusive analog circuit testing.

show abstract

A BIST-DFT technique for DC test of analog modules

Cited by 11 publications

References 18 publications

Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits

Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits

Oscillation-based testing method for detecting switch faults in High-Q SC biquad filters

A Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard

Contact Info

Product

Resources

About