A design for testability method using RTL partitioning

Hosokawa, Toshinori; Kawaguchi, K.; Ohta, Mitsuyasu; Muraoka, Michiaki

doi:10.1109/ats.1996.555142

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…However, this can be alleviated by zero-aliasing space compactor and MISR as [10]. Moreover, when this method is applied to register transfer level (RTL) partitioning [11] or scan partitioning [12], the RA can be constructed by internal resources of the CUT. Therefore, this proposed test scheme can serve as a promising alternative to IC testing.…”

Section: Discussionmentioning

confidence: 99%

An efficient controlled LFSR hybrid BIST scheme

Liu

2018

IEICE Electron. Express

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A new hybrid built-in self-test (BIST) test scheme is proposed. The test scheme consists of two components: the free LFSR mode (pseudorandom test) and the controlled LFSR mode (deterministic test). In order to improve the test quality of pseudo-random test sequence, a forward-backward pseudo-random test generation method is proposed. As every shifted-in bit is fully used to generate the most efficient test and the ratio of do not care bits is maximized in the remaining test pattern repository, the proposed controlled LFSR test generation method can find the targeted pattern with the minimal number of shift, efficiently embedding the deterministic test set into test-per-clock stream. Simulation results demonstrate that the proposed method considering for layout constraints shows great advantages in test data storage and test application time compared with previous methods.

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Section: Discussionmentioning

confidence: 99%

An efficient controlled LFSR hybrid BIST scheme

Liu

2018

IEICE Electron. Express

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“…The n-fold line-up structure includes the structure with combinational ATPG complexity. The n-fold line-up structures with large n includes the n-fold line-up structures with small n. We experimentally showed that circuits of a line-up structure are testable [8].…”

Section: N-fold Line-up Structurementioning

confidence: 99%

A partial scan design method based on n-fold line-up structures

Hosokawa

Hiraoka²,

Ohta³

et al.

Proceedings Sixth Asian Test Symposium (ATS'97)

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We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of loadhold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structures. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduce the number of test patterns by half.

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