A partial scan design method based on n-fold line-up structures

Hosokawa, Toshinori; Hiraoka, Toshihiro; Ohta, Mitsuyasu; Muraoka, Michiaki; Kuninobu, Shigeo

doi:10.1109/ats.1997.643975

“…This partial scan design method selects FFs to replace with scan FFs so that circuit structure has acyclic structure [8][9][10][11] in order to guarantee high fault efficiency. Moreover, the fault in an acyclic sequential circuit has the feature [2] that it is detectable with the number of ATPG patterns which is not more than sequential depth [2,6]+1 of the circuit.…”

Section: (2) the Basic Concept Of The Partial Scan Design Methodsmentioning

confidence: 99%

“…On the other hand, test compaction technique [10,12,13] of ATPG pattern shows that compaction efficiency becomes high if an ATPG pattern includes many don't cares (Xs). If value assignment probabilities of primary inputs are low, the probability that the values of primary inputs are Xs becomes high, so that compaction efficiency may be high.…”

Section: Examplementioning

confidence: 99%

“…In Fig.1 many primary inputs, the number of primary inputs where 0's and/or 1's are assigned to detect a certain fault at the primary output may increase. It is considered that the effect of the test pattern compaction [10,12,13] is generally low in this case. Since ALUs like multipliers do not consist of the combinational circuits of a primary output using many primary inputs, it is considered that the effect of test pattern compaction is generally high.…”

Section: Motivationmentioning

confidence: 99%

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Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Hosokawa

¹

,

Yoshimura

²

,

Ohta

³

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method. INTRODUCTIONAccording to the recent advance of semiconductor process technology, the circuit densities on LSI are growing and the automatic test design becomes more important. Because the automatic test pattern generation (ATPG) for a sequential circuit is difficult in general, a design for testability (DFT) must be applied to obtain high fault efficiency. The full scan design method [1,2] is one of popular DFT methods, so far. In the full scan design method, all flip-flops (FFs) are replaced with scan FFs. A scan FF is equivalent to a primary input and a primary output at the test mode. In the scan design method, ATPG can be performed for the portion of the circuit excluding the scan path, which is the kernel circuit. Since the kernel circuit of the full scan design LSI is a combinational one, a combinational ATPG algorithm can be applied to it and it can obtain high fault efficiency.Test application time by the scan design method is the product of the test length of an automatic test equipment (ATE) of the formula (1) and the clock period of the ATE. TL = (TP +1) × MSL + TP …(1)In the formula(1), TL is test length of an ATE, TP is the number of test patterns of the kernel circuit and is called the ATPG patterns, MSL is the maximum number of scan FFs on one scan paths and is called the maximum scan path length.As the increasing number of the external pins on LSI boundary is slower than the increase of the size of an LSI, the number of scan FFs on a scan path connected to the external pins increases relatively. Consequently, the full-scan-design test application time becomes longer. The formula (1) shows that the test length of a scan design method can be shortened by shortening the maximum scan path length and/or by reducing the number of ATPG patterns.In this paper, three DFT strategies are proposed in order to reduce test application times as follows:(1) DFT strategy1: applies the full scan design method with test point insertions to an LSI. (2) DFT strategy2: applies the partial scan design method to an LSI. (3) DFT strategy3: applies the partial scan design method with test point insertions to an LSI. The next section explains the motivation of this research. In section 3, the three DFT strategies are proposed. The effectiveness of the strategies by applying them to practical LSIs are showed in section 4. The conclusion and our future works are described in section 5. MOTIVATIONThe road map of ITRS [3] predicts that the number of gates increases at a rate of about 40% per year, and the number of externa...

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“…(2) the length of a test sequence needed in order to attain high fault efficiency, or the testing time of the LSI tester. tial circuit, high fault efficiency can be obtained with smaller hardware overheads than in full scan design [6][7][8][9]. In particular, in Ref.…”

Section: Introductionmentioning

confidence: 99%

“…In partial scan design, selection of the flip-flop (FF) of the circuit that is to be replaced by the scan FF is a major problem. It is known that test generation is possible for acyclic sequential circuits by a combinational test generation algorithm [6][7][8][9]. Hence, by selecting the scan FF in a way that makes the core circuit (the circuit after removing the scan FF) an acyclic sequen-…”

mentioning

confidence: 99%

Test sequence compaction methods for acyclic sequential circuits using a time expansion model

Hosokawa

¹

,

Inoue

²

,

Hiraoka

³

et al. 2002

Systems & Computers in Japan

0

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SUMMARYTest sequences for acyclic sequential circuits can be generated by using a time expansion model. In this paper, static and dynamic test sequence compaction techniques are proposed in which the test sequence generated by the time expansion model has two characteristics: (1) The test sequence length is constant, and (2) The location of an undefined value (X) for all primary inputs can be determined independently of test generation faults. First, a static test sequence compaction method is proposed that uses a template which is independent of the value of the test sequence. Then a dynamic test sequence compaction method is presented using reverse transform fault simulation, performing fault simulation for the time expansion model of the test pattern in which the test sequence after compaction is reverse-transformed. As a result of application of the proposed method to acyclic sequential circuits made by using partial scan design, the test sequence length was reduced by 19 to 34%.

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Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Hosokawa¹,

Yoshimura²,

Ohta³

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

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As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method. INTRODUCTIONAccording to the recent advance of semiconductor process technology, the circuit densities on LSI are growing and the automatic test design becomes more important. Because the automatic test pattern generation (ATPG) for a sequential circuit is difficult in general, a design for testability (DFT) must be applied to obtain high fault efficiency. The full scan design method [1,2] is one of popular DFT methods, so far. In the full scan design method, all flip-flops (FFs) are replaced with scan FFs. A scan FF is equivalent to a primary input and a primary output at the test mode. In the scan design method, ATPG can be performed for the portion of the circuit excluding the scan path, which is the kernel circuit. Since the kernel circuit of the full scan design LSI is a combinational one, a combinational ATPG algorithm can be applied to it and it can obtain high fault efficiency.Test application time by the scan design method is the product of the test length of an automatic test equipment (ATE) of the formula (1) and the clock period of the ATE. TL = (TP +1) × MSL + TP …(1)In the formula(1), TL is test length of an ATE, TP is the number of test patterns of the kernel circuit and is called the ATPG patterns, MSL is the maximum number of scan FFs on one scan paths and is called the maximum scan path length.As the increasing number of the external pins on LSI boundary is slower than the increase of the size of an LSI, the number of scan FFs on a scan path connected to the external pins increases relatively. Consequently, the full-scan-design test application time becomes longer. The formula (1) shows that the test length of a scan design method can be shortened by shortening the maximum scan path length and/or by reducing the number of ATPG patterns.In this paper, three DFT strategies are proposed in order to reduce test application times as follows:(1) DFT strategy1: applies the full scan design method with test point insertions to an LSI. (2) DFT strategy2: applies the partial scan design method to an LSI. (3) DFT strategy3: applies the partial scan design method with test point insertions to an LSI. The next section explains the motivation of this research. In section 3, the three DFT strategies are proposed. The effectiveness of the strategies by applying them to practical LSIs are showed in section 4. The conclusion and our future works are described in section 5. MOTIVATIONThe road map of ITRS [3] predicts that the number of gates increases at a rate of about 40% per year, and the number of externa...

show abstract

A partial scan design method based on n-fold line-up structures

Cited by 5 publications

References 17 publications

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

Test sequence compaction methods for acyclic sequential circuits using a time expansion model

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

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