A design for testability technique for quantum reversible circuits

Mondal, Joyati; Das, Debesh K.; Kole, Dipak Kumar; Rahaman, Hafizur

doi:10.1109/ewdts.2013.6673147

Cited by 6 publications

(9 citation statements)

References 16 publications

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“…Tables 3 and 4 compare the proposed design with the work in refs. [17,18,22,23,37] with respect to quantum cost overhead and the percentage detection of MMGF. In Table 3, the first four columns contain the circuit name, size, depth and quantum cost of the corresponding circuits.…”

Section: Resultsmentioning

confidence: 99%

“…The next five columns compare the quantum cost overhead of the designs in refs. [17,18,22,23,37] and the proposed design. From the table it is clear that the proposed design incurs less quantum cost overhead.…”

Section: Resultsmentioning

confidence: 99%

“…From the table it is clear that the proposed design incurs less quantum cost overhead. On average [17,18,22,23,37] incurs 154.21%, 92.77%, 165.58%, 132.16% and 122.21% overhead respectively. Whereas the proposed design incurs 80.58% overhead.…”

Section: Resultsmentioning

confidence: 99%

“…For a number of benchmark circuits, we have simulated MMGF and found the MMGF detection coverage in refs. [17,18,22,23,37] and the proposed design. The values are shown in Table 4.…”

Section: Resultsmentioning

confidence: 99%

“…The next five columns compare the percentage MMGF detection of the designs in refs. [17,18,22,23], and the proposed design. From the result it is clear that our design always provides 100% MMGF detection whereas on average [17,18,22,23] provides 97.12%, 99.6%, 99.51% and 99.38% MMGF detection.…”

Section: Resultsmentioning

confidence: 99%

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Design‐for‐testability for reversible logic circuits based on bit‐swapping

Mondal,

Das,

Bhattacharya

2023

IET Quantum Communication

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The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low‐power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k‐CNOT), k ≥ 1. While analysing testability issues in a reversible circuit, the missing‐gate fault model is often used for modelling physical defects in k‐CNOT gates. A new design‐for‐testability (DFT) technique is proposed for reversible circuits that deploys bit‐swapping using Fredkin reversible gates. It is shown that in an (n × n) circuit implemented with k‐CNOT gates, addition of only two extra inputs along with a few Fredkin gates yields easy testability in the circuit. The modified design admits a universal test set of maximum size 2n + 1 that detects all detectable missing gate faults in the original circuit, where n is the number of input/output lines in the circuit. The DFT overhead in terms of quantum cost is much less compared to that of previous approaches. The method is more advantageous for large circuits.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“…For a number of benchmark circuits, we have simulated MMGF and found the MMGF detection coverage in refs. [17,18,22,23,37] and the proposed design. The values are shown in Table 4.…”

Section: Resultsmentioning

confidence: 99%