Proceedings of the 19th ACM International Conference on Computing Frontiers 2022
DOI: 10.1145/3528416.3530232
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A design methodology for fault-tolerant computing using astrocyte neural networks

Abstract: We propose a design methodology to facilitate fault tolerance of deep learning models. First, we implement a many-core fault-tolerant neuromorphic hardware design, where neuron and synapse circuitries in each neuromorphic core are enclosed with astrocyte circuitries, the star-shaped glial cells of the brain that facilitate selfrepair by restoring the spike firing frequency of a failed neuron using a closed-loop retrograde feedback signal. Next, we introduce astrocytes in a deep learning model to achieve the re… Show more

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Cited by 13 publications
(3 citation statements)
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“…Based on their research work, 5 multipliers are reported in the high-level utilization table. A hardware cost comparison has been performed between the proposed astrocyte model in this work and two recently published articles according to different calciumbased astrocytic models in [53]- [54]. A digital design for an astrocyte model is implemented on FPGA platform which uses four DSP blocks and four block RAMs [53].…”
Section: Implementation Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…Based on their research work, 5 multipliers are reported in the high-level utilization table. A hardware cost comparison has been performed between the proposed astrocyte model in this work and two recently published articles according to different calciumbased astrocytic models in [53]- [54]. A digital design for an astrocyte model is implemented on FPGA platform which uses four DSP blocks and four block RAMs [53].…”
Section: Implementation Resultsmentioning
confidence: 99%
“…A hardware cost comparison has been performed between the proposed astrocyte model in this work and two recently published articles according to different calciumbased astrocytic models in [53]- [54]. A digital design for an astrocyte model is implemented on FPGA platform which uses four DSP blocks and four block RAMs [53]. In [54], a set of piecewise linear approximation is presented for an astrocytic-based calcium signalling with the maximum speed of 81MHz.…”
Section: Implementation Resultsmentioning
confidence: 99%
“…Lastly, neuromorphic hardware is fault-tolerant, meaning it can function even if individual components fail [26][27][28]. In traditional computing systems, individual components, such as transistors, can fail causing large portions of the system to malfunction.…”
Section: Neuromorphic Hardwarementioning
confidence: 99%