A Design of 0.7-V 400-MHz Digitally-Controlled Oscillator

Bae, Jung Nam; Radhapuram, Saichandrateja; Jo, Ikkyun; Kihara, Takao; Matsuoka, Toshimasa

doi:10.1587/transele.e98.c.1179

Cited by 6 publications

(6 citation statements)

References 20 publications

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“…The LC-tank DCO is key building block in ADPLL and it consumes most of system power for generating local frequency [1], [25], [31], [33], [35]. Therefore, ultra-low power and ultra-low voltage DCO design significantly reduces system power consumption [36], [37].…”

Section: B Digitally Controlled Oscillator (Dco)mentioning

confidence: 99%

An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO

et al. 2020

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In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is presented. For locking DCO frequency closest to the target channel, it adaptively controls capacitor banks with binary algorithm. With decrease in frequency resolution, DCO clock counts for each capacitor bank bit evaluation dynamically increases with the proposed technique for accurate frequency tracking. For compensating PVT variations and finding the BLE frequency deviation, the configurable digital DCO gain estimation is incorporated. The low power and constant current DCO operates in sub-threshold region and its power consumption is minimized by g m /I D methodology optimization, constant current source for limiting current in DCO core through adaptive low-dropout regulator (LDO) and lowering the supply voltage. The proposed design is integrated in an ADPLL for BLE transceiver and it is fabricated with 1P6M TSMC 55 nm CMOS technology. The all-digital adaptive FLL is fully synthesizable and its area is 1800 µm 2 with 1.233 K gate count. The RMS current consumption is 103.32 µA from 1 V voltage supply with 103.32 µW power requirement. The experimental results reveal, DCO draws 480 µA current from 0.55 V supply voltage at center frequency. It has frequency resolution of 4.8 kHz. The oscillator PN, FOM and FOM T at 1-MHz offset frequency from 2.44 GHz carrier frequency are −122.85 dBc/Hz, 196.38 dBc/Hz and 208.19 dBc/Hz, respectively. INDEX TERMS Adaptive controller, all-digital frequency locked loop, digitally controlled oscillator, gain estimation, constant current, LDO, ultra-low power, synthesizable.

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Section: B Digitally Controlled Oscillator (Dco)mentioning

confidence: 99%

An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO

et al. 2020

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“…A third-order feed-forward type DSM which can reduce the noise spur is utilized for precise frequency resolution. The noise transfer function NTF(z) of the employed modulator is given by [8,14]…”

Section: Ring-dcomentioning

confidence: 99%

“…Although combining discrete and continuous tuning can increase tuning range effectively [4,5], digital control tuning is an essential solution. Therefore, digitally controlled oscillator (DCO) and PLL using it, so-called all-digital PLL (ADPLL), are promising techniques for low-voltage accurate frequency generation [6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

2019

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This paper demonstrates the design and implementation of an all-digital phase-lockedloop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation techniqueto show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator(DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, whichis fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control andfractional tuning range using the DSM. The ring-DCO does not contain library-specific cells andcan be synthesized independently of the standard cell library, thus making the design portable andreducing the time required to fit for different semiconductor processes considerably. Implementedring-DCO has a wide tuning range and high-frequency resolution which meet the demands ofsystem-level integration. The ADPLL implemented in this work has the characteristics of designflexibility, a wide range of working frequency from 120 MHz to 300 MHz, and a fast responsefor achieving a locked state. The proposed ADPLL can be easily ported to different processes ina short time. The design adaptation cost is limited to adjustment of loop parameters in the code.Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable forSystem-on-Chip (SoC) applications.

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“…Because the output signal lock is selected among the 64 pre-settled signals generated by the PI, the output signal is always stabilized for small reference phase fluctuation. Figure 7 (a) shows the structure of the DCO, which consists of an LC-DCO core and digital logic blocks with two types of digital words (In int and In frac) for frequency tuning [16]. A thermometer coder employing dynamic element matching (DEM) is used to convert the input digital bit.…”

Section: Phase Interpolatormentioning

confidence: 99%

A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

Bae

Radhapuram

et al. 2016

IEICE Trans. Electron.

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A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm 2 , consumes 840 μW from a 0.7-V supply voltage, and has a settling time of 80 μs. The phase noise was measured to be −114 dBc/Hz at an offset frequency of 200 kHz.

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A Design of 0.7-V 400-MHz Digitally-Controlled Oscillator

Cited by 6 publications

References 20 publications

An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO

An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

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