A Design of Diode-Clamped 11-Level Inverter and Its Harmonic Effect on Transformer Losses

Astomo, Reynanda Bagus Widyo; Ashari, Mochamad; Soedibyo,

doi:10.1109/isitia49792.2020.9163696

Cited by 2 publications

(3 citation statements)

References 13 publications

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“…To demonstrate the feature discussed in the previous section, a comparative analysis is performed in this section against some of the recent topologies [4, 5, 10, 16–22]. The comparison is done on the basis of the available number of switches, number of diodes, number of capacitors, voltage gain, TSV, and PIV.…”

Section: Comparative Studymentioning

confidence: 99%

“…In case of [17, 18, 20], there is no need of a capacitor to produce the staircase output but they require higher number of dc sources as compared to the proposed topology. The topology presented in [16, 19] produces the same level of output but requires more and diode in comparison to the proposed topology. In case of MLIs elaborated in [21, 22], using less dc sources and requires no diode, however, to produce output voltage of 11‐level the required switches as well as capacitance are much more than the proposed MLI.…”

Section: Comparative Studymentioning

confidence: 99%

“…In which, the H-bridge at the backend and switched capacitor at the frontend are used to generate the output. A similar approach has been adopted in the topologies of [16][17][18][19][20][21][22], however, the device count has been the limiting factor for these topologies. In this work, a dual-source dc to ac converter topology has been presented.…”

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confidence: 99%

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11 Level boost inverter topology with dual‐source configuration

Siddique

Wasiq

Iqbal

et al. 2022

IET Power Electronics

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With the advancement of the application of power converters in the power industry, the research towards the prominent power converter namely multilevel inverter has gained a lot of attraction. Here, a dual‐source configured 11 level inverter topology is being discussed, which uses nine power semiconductor devices and one capacitor. The proposed topology is able to charge the capacitor up to 2Vdc which provides the boosting feature with the voltage gain of 1.67. An extended comparison with several other topologies has been provided which highlights the major contribution of the work. A low‐power laboratory prototype has been used for the validation of the proposed 11 level topology. Further, a thorough assessment of comparable topologies has been conferred in detail.

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Section: Comparative Studymentioning

confidence: 99%