Multilevel inverters are a new family of converters for dc-ac conversion for the medium and high voltage and power applications. In this paper, two new topologies for the staircase output voltage generations have been proposed with a lesser number of switch requirement. The first topology requires three dc voltage sources and ten switches to synthesize 15 levels across the load. The extension of the first topology has been proposed as the second topology, which consists of four dc voltage sources and 12 switches to achieve 25 levels at the output. Both topologies, apart from having lesser switch count, exhibit the merits in terms of reduced voltage stresses across the switches. In addition, a detailed comparative study of both topologies has been presented in this paper to demonstrate the features of the proposed topologies. Several experimental results have been included in this paper to validate the performances of the proposed topologies with different loading condition and dynamic changes in load and modulation indexes. INDEX TERMS Asymmetric, hybrid inverter, inverter topology, multilevel inverter, MLI, nearest level control, power electronics, single-phase inverter, reduce switch count.

Multilevel inverters (MLIs) are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single-phase cascaded MLI topology is suggested in this paper. The proposed MLI topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and a number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable MLI topologies to prove the superiority of the proposed structure. A selective harmonic elimination pulse width modulation technique is used to produce the pulses for the switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and for cascading of two such units to achieve 71 levels at the output. INDEX TERMS Basic unit, cascaded inverter, multilevel inverter (MLI), selective harmonic elimination, SHEPWM, optimization, reduce switch count. II. ANALYSIS AND DESCRIPTION OF PROPOSED MULTILEVEL TOPOLOGY A. BASIC UNIT OF PROPOSED TOPOLOGY

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The inceptions of multilevel inverters (MLI) have caught the attention of researchers for medium and high power applications. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single-phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 levels at the output with three dc voltage sources and eight switches. Three extentions of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, resulting in a maximum efficiency of 98.5%. Nearest level control (NLC) pulse-width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to show the feasibility of the proposed MLI topology.INDEX TERMS DC-AC converter, multilevel inverter, reduce switch count, nearest level control (NLC).

Based on the concept of switched-capacitor based multilevel inverter topology, a new structure for a boost multilevel inverter topology has been recommended in this paper. The proposed topology uses 11 unidirectional switches with a single switched capacitor unit to synthesize nine-level output voltage waveform. Apart from the twice voltage gain, self-voltage balancing of capacitor voltage without any auxiliary method along with reduced voltage stress has been the main advantages of this topology. The merits of proposed topology have been analyzed through various comparison parameters including component counts, voltage stresses, cost and efficiency with a maximum value of 98.3%, together with the integration of switched capacitors into the topology following recent development. Phase disposition pulse width modulation (PD-PWM) technique and nearest level control PWM (NLC-PWM) have been used for the control of switches. Different simulation and hardware results with different operating conditions are included in the paper to demonstrate the performance of the proposed topology. INDEX TERMS Multilevel inverter, boost inverter topology, switched-capacitor, single dc source, reduce switch count, PWM.