A New Single Phase Single Switched-Capacitor Based Nine-Level Boost Inverter Topology With Reduced Switch Count and Voltage Stress

Abstract

Based on the concept of switched-capacitor based multilevel inverter topology, a new structure for a boost multilevel inverter topology has been recommended in this paper. The proposed topology uses 11 unidirectional switches with a single switched capacitor unit to synthesize nine-level output voltage waveform. Apart from the twice voltage gain, self-voltage balancing of capacitor voltage without any auxiliary method along with reduced voltage stress has been the main advantages of this topology. The merits of proposed topology have been analyzed through various comparison parameters including component counts, voltage stresses, cost and efficiency with a maximum value of 98.3%, together with the integration of switched capacitors into the topology following recent development. Phase disposition pulse width modulation (PD-PWM) technique and nearest level control PWM (NLC-PWM) have been used for the control of switches. Different simulation and hardware results with different operating conditions are included in the paper to demonstrate the performance of the proposed topology. INDEX TERMS Multilevel inverter, boost inverter topology, switched-capacitor, single dc source, reduce switch count, PWM.

Single-Stage Three-Phase Grid-Tied Isolated SEPIC-Based Differential Inverter With Improved Control and Selective Harmonic Compensation

“…From (17,18), the power losses of both capacitors are obtained as: Where, is the ESR resistance of the capacitor. Finally, the losses of other components such as control circuit, snubber circuit of HFL transformer and connecting wires can be obtained from [58][59][60][61].…”

“…This topology processes the power twice (two-stage inverters), which are extensively studied and adds many limitations for the component count and the control complexity. During the last decade, many topologies have been introduced using the same approach, such as switched-capacitor based inverters [18][19][20][21][22][23][24], Z source inverters [25][26][27][28][29], and multi-level inverters [30][31][32].…”

“…This circuit can charge and discharge in parallel and series to boost the input DC voltage. However, this topology has many component counts, especially at the three-phase systems [18][19][20][21], and lacks galvanic isolation and modular construction [23]. Also, it has many issues related to the capacitors' mismatch and their selfvoltage balancing [24].…”

Improved “K” type seven‐level switched capacitor inverter topology with Self‐voltage balancing

“…It is of importance to mention that the numbers of charging and discharging of floating capacitor are equal in the aforementioned works. 4,5,17,18 In Siddique et al 6,7 a new seven ANPC topology with voltage boosting of 1.5 times higher than the input voltage is presented. In their study, 8 Sathik et al successfully present a topology with triple voltage boosting.…”

An improved asymmetrical multilevel inverter topology with reduced semiconductor device count

“…The diode clamped multilevel converter includes a higher number of diodes which suffers from the main drawback of voltage unbalancing in capacitors. To get rid of the voltage unbalancing problem two improved topologies have been proposed in References 6‐8, in which the authors had used the switched capacitors approach to remove the capacitor voltage unbalancing problem. Moreover, the topology also possesses voltage boosting ability.…”