Summary In this paper, a modified and improved high gain dc–dc boost converter is proposed. The converter has utilized two voltage multiplier cells (VMCs) comprising switched capacitors (SC) and switched inductors (SL) to increase the voltage gain of the converter. The basic concept of these switched topologies is that when the switch is ON, the energy is stored by the inductor and the capacitor transfers its energy to load and inductor. In the OFF cycle, the inductor transfers its energy to the capacitor, and, simultaneously, capacitor is charged through input voltage also. As compared to other nonisolated topologies, the proposed converter has a high voltage gain and low voltage stress across semiconductor devices. The voltage stress on all capacitors except the output capacitor is less than the voltage across the load. A detailed analysis of the converter in continuous conduction (CCM) and discontinuous conduction modes (DCM) is shown. The proposed converter has a peak efficiency of 94.8%. For the efficiency calculation of the proposed topology, PLECS software is used. The experimental results agree with the theoretical analysis and validate the working and performance of the proposed converter.

To overcome the problems associated with Z-source-based DC-DC converters, a quasi-Z-source (QZS)-based high-gain DC-DC boost converter with switched capacitors is proposed in this work. Z-source-based DC-DC converters have problems like low-voltage gain, discontinuous input current, and high-voltage stress on the active and passive components. The proposed converter can produce a high-voltage gain of more than 10 times for a duty cycle of less than 0.5. The converter has other desirable features like reduced voltage stress across the switching components and continuous input current (CIC). It comprises a QZS cell made up of switched inductors and a voltage multiplier cell (VMC) made up of switched capacitors. The power loss analysis is done using PLECS software by incorporating the real parameters of switches and diodes from the datasheet. A hardware prototype of 200 W is developed in the laboratory to verify the working of the converter. In experimental results for an output power of 200 W, the converter is operated with a source voltage of 33 V at a duty ratio of 0.4 providing an output voltage of 395 V. The converter performance is good in open-loop conditions and is verified through experimental results. K E Y W O R D S duty ratio (λ), quasi-Z-source (QZS), voltage multiplier cell (VMC), voltage stress | INTRODUCTIONNowadays, gain DC-DC converters have found applications in electric vehicles (EVs), DC microgrids, switch-mode power supplies, and robotics to name a few. The power range of these high-gain converters varies from few milliwatts to a kilowatt range. The main objective is to build a topology with a high gain and reduced number of components. Desirable features like low voltage and current stress, common ground with low ripple in input current make the highgain converter an attractive choice for renewable energy applications. Conventional step-up converters and their variants need to be operated at a high duty ratio (λ) to obtain high-voltage gain. Consequently, the efficiency decreases, and the stress across the components increases. Moreover, the low and fluctuating output voltage of the PV panel cannot be fed to the inverter directly; it must be boosted with reduced ripple using a high-gain converter. 1,2 In Figure 1, it is depicted that a high-gain DC-DC converter can effectively boost the voltage from various sources like fuel cells, solar PV modules, battery, and an ultra-capacitor. These converters are used at the front end of a grid-connected inverter to maintain the DC-link voltage. The DC-DC converters have isolated and non-isolated structures. The isolated structures

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Background Multilevel Inverters have become a viable alternative to two‐level inverters because of their superior power quality, however, the increase in number of switches with their corresponding voltage stress, and dc voltage sources are the major factors for higher number of levels. Aim This paper proposes a modified and improved asymmetrical multilevel inverter with 15 output voltage levels. Materials and Methods The distinguishing feature of the proposed topology is the reduced number of switches as compared to recently introduced topologies having the same number of levels. As the number of devices has a direct relation to the cost of the inverter, therefore, reducing the devices will decrease the cost and makes the system more reliable for use in potential applications. The three different extensions of the proposed circuit is also discussed in the paper. Nearest level control technique is used as a modulation strategy to control the output voltage of the proposed topology. Results and Discussion The proposed Multilevel Inverter (MLI) has been simulated in MATLAB/SIMULINK environment. The THD analysis is also shown in the paper. Experimental results have been presented and discussed to validate the obtained simulation results. Power Loss analysis of the converter is also provided. It is done with the help of PLECS software. Conclusion The presented topology have lesser value of total standing voltage (TSV) and at the same time, there is no requirement of an H‐bridge in the structure to achieve polarity reversal for the desired levels.

This paper presented an improved asymmetrical multilevel inverter module with reduced switches count. The basic module is capable of producing 15 level outputs with four dc sources and 10 switches. The proposed topology has an inherent ability to generate negative voltage levels, made it possible to utilize lower rating switches, and has lower total standing voltage. To have more number of levels, a series-connected cascade extension of the module has been done. The three different algorithms for selecting the magnitude of dc sources are proposed. The generalized relations for different parameters are based on the number of added basic units and the number of presented levels for each source selection algorithm. Nearest level control (NLC) is used as the modulation technique. A comparative study shows that the developed topology outperformed other selected existing topologies on many parameters. The performance of the module is evaluated through detailed simulation and power loss analysis. Accuracy of the obtained simulation results is validated through proper experimental testing of the circuit in the laboratory. K E Y W O R D Sasymmetrical multilevel inverter, nearest level control, power loss analysis, total harmonic distortion (THD)