A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits

Ibrayev, Timur; James, Alex Pappachen; Merkel, Cory; Kudithipudi, Dhireesha

doi:10.1109/iscas.2016.7527475

Cited by 21 publications

(34 citation statements)

References 8 publications

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“…that are spatially similar) are grouped together into a common output representation. Recently there has been increasing interest in the mathematical properties of the HTM spatial pooler (Pietroń et al, 2016;Mnatzaganian et al, 2017) and machine learning applications based on it (Thornton and Srbic, 2011;Ibrayev et al, 2016). In this paper we explore several functional properties of the HTM spatial pooler that have not yet been systematically analyzed.…”

Section: Introductionmentioning

confidence: 99%

“…HTM spatial pooler is an important component of HTM and was originally described in the Numenta whitepaper (Hawkins et al, 2011). Recently there has been an increasing interest in the mathematical properties of the HTM spatial pooler (Mnatzaganian et al, 2016;Pietroń et al, 2016) and machine learning applications based on it (Thornton and Srbic, 2011;Ibrayev et al, 2016). However, the computational properties and design principles of HTM spatial pooler have not been well documented.…”

Section: Introductionmentioning

confidence: 99%

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The HTM Spatial Pooler – a neocortical algorithm for online sparse distributed coding

Cui

Ahmad

Hawkins

2016

Preprint

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1.AbstractHierarchical temporal memory (HTM) provides a theoretical framework that models several key computational principles of the neocortex. In this paper we analyze an important component of HTM, the HTM spatial pooler (SP). The SP models how neurons learn feedforward connections and form efficient representations of the input. It converts arbitrary binary input patterns into sparse distributed representations (SDRs) using a combination of competitive Hebbian learning rules and homeostatic excitability control. We describe a number of key properties of the spatial pooler, including fast adaptation to changing input statistics, improved noise robustness through learning, efficient use of cells and robustness to cell death. In order to quantify these properties we develop a set of metrics that can be directly computed from the spatial pooler outputs. We show how the properties are met using these metrics and targeted artificial simulations. We then demonstrate the value of the spatial pooler in a complete end-to-end real-world HTM system. We discuss the relationship with neuroscience and previous studies of sparse coding. The HTM spatial pooler represents a neurally inspired algorithm for learning sparse representations from noisy data streams in an online fashion.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The HTM Spatial Pooler – a neocortical algorithm for online sparse distributed coding

Cui

Ahmad

Hawkins

2016

Preprint

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“…In the original algorithm, the parameter k, can be adjusted to regulate the desired number of winning columns [17]. However, to simplify the algorithm for the circuit level implementation, the value of the desired activity level is limited to 1 because the the inhibition phase is implemented by the Winner-Takes-All (WTA) circuits [10], [11].…”

Section: A Htm Overviewmentioning

confidence: 99%

“…B. Analog Implementation 1) Memristor-CMOS Hybrid Implementation of SP: One of the first works that presented the analog implementation of Spatial Pooler is based on memristor-CMOS hyrbrid circuit [10]. Similar to any neural circuit, SP design requires implementation of the synapse that allows for communication between the neurons.…”

Section: A Mixed-signal Htm Implementationmentioning

confidence: 99%

Hierarchical Temporal Memory Using Memristor Networks: A Survey

Krestinskaya

Dolzhikova

James

2018

IEEE Trans. Emerg. Top. Comput. Intell.

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This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed.

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“…[18] proposed single synapse circuit with specific intentions to precisely model synapse as it is explained and used within HTM framework. Figure 4 illustrates the circuit design of the single synapse, which can be divided into four parts: input current mirror, memristor, buffer, and voltage-to-current converting NMOS.…”

Section: Single Synapse Circuit Realizations Using Memristor Devicesmentioning

confidence: 99%

Introduction to Memristive HTM Circuits

James¹,

Ibrayev²,

Krestinskaya³

et al. 2018

Memristor and Memristive Neural Networks

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Hierarchical temporal memory (HTM) is a cognitive learning algorithm intended to mimic the working principles of neocortex, part of the human brain said to be responsible for data classification, learning, and making predictions. Based on the combination of various concepts of neuroscience, it has already been shown that the software realization of HTM is effective on different recognition, detection, and prediction making tasks.However, its distinctive features, expressed in terms of hierarchy, modularity, and sparsity, suggest that hardware realization of HTM can be attractive in terms of providing faster processing speed as well as small memory requirements, on-chip area, and total power consumption. Despite there are few works done on hardware realization for HTM, there are promising results which illustrate effectiveness of incorporating an emerging memristor device technology to solve this open-research problem. Hence, this chapter reviews hardware designs for HTM with specific focus on memristive HTM circuits.

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A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits

Cited by 21 publications

References 8 publications

The HTM Spatial Pooler – a neocortical algorithm for online sparse distributed coding

The HTM Spatial Pooler – a neocortical algorithm for online sparse distributed coding

Hierarchical Temporal Memory Using Memristor Networks: A Survey

Introduction to Memristive HTM Circuits

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