A design of Reed-Solomon decoder with systolic-array structure

Iwamura, Keiichi; Dohi, Y.; Imai, Hideki

doi:10.1109/12.368005

Cited by 19 publications

(10 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The Systolic Array architecture has been applied to the regular and iterative VLSI architecture, like RS encoders and decoders, and showed good performance [10]. The systematic design approach of a Systolic Array Processor can make the circuit design easy for implementation and do the pipelining to fit the system level design specifications.…”

Section: Introductionmentioning

confidence: 99%

A NAND Flash Memory Controller for SD/MMC Flash Memory Card

Lin¹,

Chen²,

Wang³

et al. 2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

View full text Add to dashboard Cite

In this paper, a novel NAND Flash Memory Controller was designed. A t-EC w-bit Parallel BCH ECC code was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND type Flash memory. A Code-Banking mechanism was designed for the trade-offs between the controller cost and the ISP (In System Programmability) support. With the ISP functionality and the Flash Parameters programmed in the reserved area of the Flash Memory chip during the card production stage, the function for supporting various kinds of NAND Flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual Channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real SD/MMC flash memory card controller chip was designed and implemented with UMC 0.18um CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.

show abstract

Section: Introductionmentioning

confidence: 99%

A NAND Flash Memory Controller for SD/MMC Flash Memory Card

Lin¹,

Chen²,

Wang³

et al. 2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

View full text Add to dashboard Cite

show abstract

“…To reduce a hardware size, the VLSI design of the RS decoder using a systolic array has been proposed in [5,6] and a pipelined RS decoder has been proposed in [7, [9,101. This paper proposes a simple pipeline RS decoder which uses the Euclid's algorithm to reduce the decoding latency and the hardware complexity.…”

Section: Introductionmentioning

confidence: 99%

Design of an area efficient Reed-Solomon decoder ASIC chip

Chang

Sunwoo²

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

View full text Add to dashboard Cite

Abstracf -This paper describes an area efficient pipelined Reed-Solomon (RS) decoder.We propose two simple basic cell architectures which evaluate the error locator and the error magnitude polynomial in the general Euclid's algorithm. The evaluation involves high computational complexity, and thus, it affects the speed and the hardware complexity of RS decoders. The proposed architectures can reduce the hardware complexity by more than 16% of existing RS decoder architectures. The proposed RS decoder can be programmed to decode four RS codes defined in Galois field 28, i.e., (200,188), (120, lOS), (60,48), and (40,28) and can correct up to six errors. The fabricated FEC (Forward Error Correction) chip including the RS and Viterbi decoders operates at 40 MHz. The total number of gates for the RS decoder is about 31,000 and the FEC chip contains about 76,000 gates. 0-7803-5650-0/99/$10.00 Q 1999 IEEE

show abstract

“…Secondly PEs in [1] use multiplexers to switch between the RS procedures which results in a complex architecture.…”

Section: Rs Decoder Blockmentioning

confidence: 99%

“…The architecture is devised by an extension of the concepts described in references [1] - [4] to achieve the features of low complexity, high speed, regularity and flexibility.…”

Section: Rs Decoder Blockmentioning

confidence: 99%

See 1 more Smart Citation

A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication

Rashid

Fitzek

Olsen

et al.

2006 IEEE Design and Diagnostics of Electronic Circuits and Systems

View full text Add to dashboard Cite

Abstract-This paper proposes a low complexity, high speed, regular and flexible architecture for VLSI implementation of Reed Solomon decoder. With this architecture the error locator and error evaluator polynomials of the decoder can be computed in parallel and the same datapath can be reused to realize a partially pipelined parallel RS decoder. By architecture reuse the number of required resources for the RS decoder can be adjusted to a specific application, while maintaining internal parallel computation of each RS procedure. The resulting architecture contains one type of program element, which simplifies test and fabrication.

show abstract

A design of Reed-Solomon decoder with systolic-array structure

Cited by 19 publications

References 11 publications

A NAND Flash Memory Controller for SD/MMC Flash Memory Card

A NAND Flash Memory Controller for SD/MMC Flash Memory Card

Design of an area efficient Reed-Solomon decoder ASIC chip

A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication

Contact Info

Product

Resources

About