A Design of Versatile Image Processing Platform Based on the Dual Multi-core DSP and FPGA

Zhan, Zhenhuan; Hao, Wei; Tian, Yan; Yao, Da-wei; Xianhong, Wang

doi:10.1109/iscid.2012.210

Cited by 11 publications

(5 citation statements)

References 7 publications

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“…In the related research on signal processors, Palmese studied a beamforming algorithm based on the CZT in uniform linear arrays and planar arrays [ 22 ], and then deduced its analytical formula in near field in detail [ 23 ]. Zhan introduced the method of high-speed serial communication between a FPGA and DSP through SRIO [ 24 ]. Yang used multiple DSP chips to form a signal processing array to achieve high-precision sonar imaging [ 25 ].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP

Tian

Guo

Zhao

et al. 2021

Sensors

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Aiming at addressing the contradiction between the high-speed real-time positioning and multi-channel signal processing in multi-beam sonar systems, in this work we present a real-time multi-beam sonar system based on a Field Programmable Gate Array (FPGA) and Digital Signal Processing (DSP) from two perspectives, i.e., hardware implementation and software optimization. In terms of hardware, an efficient high-voltage pulse transmitting module and a multi-channel data acquisition module with time versus gain (TVG) compensation with characteristics such as low noise and high phase amplitude consistency, are proposed. In terms of algorithms, we study three beamforming methods, namely delay-and-sum (D&S), direct-method (DM) and Chirp Zeta Transform (CZT). We compare the computational efficiency of DM and CZT in the digital domain. In terms of software, according to the transmission bandwidth of the Gigabit Ethernet and a serial rapid IO (SRIO) interface, the data transmission paths of the acquired data and the beam pattern between the FPGA, the DSP, and a personal computer (PC) are planned. A master-slave multi-core pipelined signal processing architecture is designed based on DSP, which enhances the data throughput of the signal processor by seven times as compared with that of the single-core operation. The experimental results reveal that the sound source level of the transmitting module is around 190.25 dB, the transmitting beam width is 64° × 64°, the background noise of the acquisition module is less than 4 μVrms, the amplitude consistency error of each channel is less than −6.55 dB, and the phase consistency error is less than 0.2°. It is noteworthy that the beam number of the sonar system is 90 × 90, the scanning angle interval is 0.33°, the working distance ranges from 5 m to 40 m, and the maximum distance resolution is 0.384 m. In the positioning experiment performed in this work; the 3-D real-time position of the baffle placed in the detection sector is realized. Please note that the maximum deviation of azimuth is 2°, the maximum deviation of elevation is 2.3°, and the maximum distance deviation is 0.379 m.

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Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP

Tian

Guo

Zhao

et al. 2021

Sensors

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“…This paper selects the serial RapidIO (SRIO) interface for data transmission between the Master DSP and FPGA [20]. SRIO is a high-speed serial protocol, and its interface can choose from three different link channel widths: 1×, 2×, and 4×.…”

Section: Srio Controllermentioning

confidence: 99%

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

Zhang,

Liu,

et al. 2024

Electronics

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The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

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“…Other alternatives propose using systems composed of digital signal processing (DSP) elements known for providing high performance and low response times in multimedia processing [38], [39]. DSP and reconfigurable systems were also proposed to combine these two aspects and build versatile systems with high-throughput architectures that integrate into the same system [40].…”

Section: B Multimedia Architecturesmentioning

confidence: 99%

Distributed Architectures for Intensive Urban Computing: A Case Study on Smart Lighting for Sustainable Cities

et al. 2019

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New information and communication technologies have contributed to the development of the smart city concept. On a physical level, this paradigm is characterized by deploying a substantial number of different devices that can sense their surroundings and generate a large amount of data. The most typical case is image and video acquisition sensors. Recently, these types of sensors are found in abundance in urban spaces and are responsible for producing a large volume of multimedia data. The advanced computer vision methods for this type of multimedia information means that many aspects can be dynamically monitored, which can help implement value-added applications in the city. However, obtaining more elaborate semantic information from these data poses significant challenges related to a large amount of data generated and the processing capabilities required. This paper aims to address these issues by using a combination of cloud computing technologies and mobile computing techniques to design a three-layer distributed architecture for intensive urban computing. The approach consists of distributing the processing tasks among a city's multimedia acquisition devices, a middle computing layer, known as a cloudlet, and a cloud-computing infrastructure. As a result, each part of the architecture can now focus on a small number of tasks for which they are specially designed, and data transmission communication needs are significantly reduced. To this end, the cloud server can hold and centralize the multimedia analysis of the processed results from the lower layers. Finally, a case study on smart lighting is described to illustrate the benefits of using the proposed model in smart city environments. INDEX TERMS Mobile cloud computing, data processing, distributed architectures, smart city, urban computing.

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A Design of Versatile Image Processing Platform Based on the Dual Multi-core DSP and FPGA

Cited by 11 publications

References 7 publications

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

Distributed Architectures for Intensive Urban Computing: A Case Study on Smart Lighting for Sustainable Cities

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