A design system for on-chip oversampling A/D interfaces

Mar, M.; Brodersen, R.W.

doi:10.1109/92.406993

Cited by 8 publications

(3 citation statements)

References 36 publications

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“…15. The ideal behavior of this circuit is described by the following differential equation: (7) where is the input voltage, is the input current (provided by the feedback DAC block), and is a state variable, which can be integrated by the SIMULINK solvers very efficiently [15]. Fig.…”

Section: Behavioral Modeling Of Ct Building Blocksmentioning

confidence: 99%

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High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

Ruiz-Amaya

Rosa

Fernandez

et al. 2005

IEEE Trans. Circuits Syst. I

126

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This paper presents a high-level synthesis tool for 61 modulators (61 s) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for 61 synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of 61 s using both discrete-time and continuous-time circuit techniques.

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Section: Behavioral Modeling Of Ct Building Blocksmentioning

confidence: 99%

“…• Knowledge-based synthesis tools, which are based on capturing the knowledge of experienced designers [6], [7]. Although the execution times are very short, the results still must be optimized because design procedures are usually based on approximate equations and very simple models.…”

Section: Introductionmentioning

confidence: 99%

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

Ruiz-Amaya

Rosa

Fernandez

et al. 2005

IEEE Trans. Circuits Syst. I

126

View full text Add to dashboard Cite

show abstract

“…• Knowledge-based synthesis-tools, which are based on capturing the knowledge of experienced designers [4] [5]. Although the execution times are very short, the results still must be optimized because design procedures are usually based on approximate equations and very simple models.…”

Section: Introductionmentioning

confidence: 99%

MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time ΣΔ modulators

Ruiz-Amaya¹,

Rosa²,

Medeiro³

et al.

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of Modulators ( Ms). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of Ms using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques (*) .

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Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology

Medeiro

Pérez-Verdú

Rosa

et al. 1997

Int. J. Circ. Theor. Appl.

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This paper uses a CAD methodology proposed by the authors to design a low‐power second‐order ΣΔM. This modulator has been fabricated in a 0·7 μm CMOS technology to be used as the front‐end of an energy‐metering mixed‐signal ASIC and features 16·4 bit at a digital output rate of 9·6 kHz with a power consumption of 1·71 mW. It yields a value of the power(W)/(2Resolution(bit)×output rate (Hz)) figure which is the smallest reported to now, thus demonstrating the possibility to design high‐performance embeddable ΣΔMs using CAD methodologies. © 1997 by John Wiley & Sons, Ltd.

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A design system for on-chip oversampling A/D interfaces

Cited by 8 publications

References 36 publications

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time ΣΔ modulators

Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology

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