A design tradeoff study with monolithic 3D integration

Abstract

Abstract-This paper studies various design tradeoffs existing in the monolithic3Dintegrationtechnology.Differentdesignstylesinmonolithic 3D ICs are studied, including transistor-level monolithic integration (MI-TR) and gate-level integration (MI-G). GDSII-level layout of monolithic 3D designs are constructed and analyzed. Compared with its 2D counterparts, MI-TR designs have advantages in footprint area, wire-length, timing, and power, because of the smaller footprint. MI-G design style also demonstrate advantages in area, timing and power over TSV-based designs, because of the smaller size and parasitics of inter-tier vias compared with TSVs. To further take the advantage of monolithic 3D technology, several technology improvement options are also explored. Besides, some possible design challenges with monolithic 3D are also studied, including global variation and signal integrity issues.

Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground TSV Shielding

“…The series inductance L Rect,S for a rectangular cross section is expressed as in (12), where l Rect is the length of rectangular interconnects. The mutual inductance due to nearby rectangular interconnects as expressed in (13) can be calculated from the geometric mean distance between two conductors, which is approximately equal to the distance between the track centers using the Greenhouse formula [22] …”

“…The simulation and analytical results are compared for an inductance up to 3 nH and the variation is found within 5%, which supports that the approximations considered in the test case are reasonable. Each term in (20) is computed based on expressions (8), (9), and (12). Similarly, the 3-D inductor resistance expression becomes…”

“…Recently, monolithic integration has become popular for gate-level or transistor-level 3-D IC integration due to its very small intertier via (50 nm in diameter) and very high density vias. Although these intertier vias have the potential for very small ON-chip inductor realization, the fabrication process is complicated and needs to be standardized for inductor fabrication with the CMOS process [12]. With modern DRIE technology, TSV fabrication with very high aspect ratio (>100) was possible to achieve [13].…”

Enabling area efficient RF ICs through monolithic 3D integration

“…Various design methodologies for M3D digital circuits have been proposed so far, [5], [6]. To the best of our knowledge there is no prior work on M3D integration for RF/AMS ICs.…”

Design challenges and solutions for ultra-high-density monolithic 3D ICs

“…In this design style, each standard cell is redesigned such that its PMOS and NMOS are on different tiers [3], [4], [5]. As in the case of SRAM, the advantage of doing this is that the PMOS and NMOS can be optimized separately.…”