In this paper, we present a novel through-siliconvia (TSV)-based 3-D inductor structure with ground TSV shielding for better noise performance. In addition, a circuit model is proposed for the inductor, which can reduce the simulation time over finite-element-based 3-D full-wave simulation. Rigorous 3-D full-wave simulation is performed up to 10 GHz to validate the circuit model. The ground TSV-based 3-D inductor is found to be resilient to TSV-TSV crosstalk noise compared with conventional 3-D inductors. The simulation results revealed that more than −33 dB of isolation can be achieved at 2 GHz between the 3-D inductor and the noise probe.Index Terms-3-D full wave simulation, 3-D inductor, crosstalk, through-silicon-via (TSV) shielding.
Abstract:In the fault diagnosis system using empirical mode decomposition (EMD), it is important to select the intrinsic mode functions (IMFs) which contain as much fault information as possible and to alleviate the problems of mode mixing and spurious modes. An effective solution to these problems in the decomposition process can help to determine significant IMFs and to improve the performance of the fault diagnosis system. This paper describes a novel power-based IMF selection algorithm and evaluates the performance of the proposed fault diagnosis system using improved complete ensemble EMD with adaptive noise and a multi-layer perceptron neural network.
As the density of memories increases, unwanted interference between cells and the coupling noise between bit‐lines become significant, requiring parallel testing. Testing high‐density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built‐in self‐test (BIST) algorithm for neighborhood pattern‐sensitive faults (NPSFs) and new neighborhood bit‐line sensitive faults (NBLSFs). Instead of the conventional five‐cell and nine‐cell physical neighborhood layouts to test memory cells, a four‐cell layout is utilized. This four‐cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck‐at faults, transition faults, conventional pattern‐sensitive faults, and neighborhood bit‐line sensitive faults.
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