As the density of memories increases, unwanted interference between cells and the coupling noise between bit‐lines become significant, requiring parallel testing. Testing high‐density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built‐in self‐test (BIST) algorithm for neighborhood pattern‐sensitive faults (NPSFs) and new neighborhood bit‐line sensitive faults (NBLSFs). Instead of the conventional five‐cell and nine‐cell physical neighborhood layouts to test memory cells, a four‐cell layout is utilized. This four‐cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck‐at faults, transition faults, conventional pattern‐sensitive faults, and neighborhood bit‐line sensitive faults.