A DFT method for BIST of RTL data paths based on single‐control testability

Abstract

SUMMARYIn this paper, as a built-in self-test (BIST) scheme for register transfer level data paths, we will propose a BIST of the test per clock scheme based on hierarchical testing. In this technique, test pattern generators and response analyzers are added only to primary inputs and primary outputs of circuit under test; and for the respective combinational circuit elements, the test patterns and corresponding responses are propagated by using paths on a data path. In this paper, as a data path capable of BIST based on this hierarchical testing, we will define a single-control testable data path, and propose a design for testability method for changing the design from a given data path to a single-control testable data path. Moreover, the evaluation of the proposed technique is performed using benchmark circuits.

Hierarchical BIST: Test‐per‐clock BIST with low overhead

“…In this paper, we propose a method based on Single Control (SC) testability [5] and Concurrent Single Control testability (CSC) [6] for the datapath at the register-transfer level (RTL); we call our method Time-division Concurrent Single Control testability (TCSC). SC, CSC, and our method are all different means by which one can implement hierarchical BIST.…”