A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point

Rust, Ingo; Noll, Tobias G.

doi:10.1109/issoc.2010.5625547

Cited by 6 publications

(9 citation statements)

References 10 publications

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“…Even if the same circuit is implemented in different technology, the power consumption is obviously different. In Table 4, the power consumption of [13,16] implemented in 90 nm technology is about nine times than [14,15]. However, even compared with [14,15], which are implemented in 40 nm technology, the proposed structure also achieves lower dynamic power under the same calculation cycles and precision.…”

Section: Implement Results and Comparisonmentioning

confidence: 99%

“…In Table 4, the power consumption of [13,16] implemented in 90 nm technology is about nine times than [14,15]. However, even compared with [14,15], which are implemented in 40 nm technology, the proposed structure also achieves lower dynamic power under the same calculation cycles and precision. Therefore, the proposed square-root structure is also suitable for power sensitive processor design.…”

Section: Implement Results and Comparisonmentioning

confidence: 99%

“…In the proposed algorithm the estimated partial square-root digits w * can be expressed as (13), where S * = d and U * i is the estimated partial remainder with L bit-width, and the calculation process of U * i can be expressed as (14), where U * 0 = P − S * = ∆p.…”

Section: The Proposed Square-root Algorithmmentioning

confidence: 99%

“…In order to obtain a better timing performance, the structure of estimation circuit is improved in this paper. First, for the estimation process of each square-root digit in (14), the composite adder is used instead of the full-adder, so that the addition and subtraction are carried out independently, and the result of the addition/subtraction operation is selected according to the sign of the previous stage. The carry-in delay of full-adder is reduced.…”

Section: Proposed Square-root Architecturementioning

confidence: 99%

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A Low-Cost High Radix Floating-Point Square-Root Circuit

2021

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In this paper, we propose an efficient architecture of floating-point square-root circuit with low area cost, which is in accordance with the IEEE-754 standard. We extend the principle of the standard SRT algorithm so that the latency and area cost of the proposed circuit are linear with the radix. In addition, no extra computation cycles are required. With 65 nm technology, the area cost of the single-precision floating-point square-root circuit based on proposed architecture is only 6450.84 μm2, and the dynamic power consumption is only 0.764 mW at 300 MHz. The implementation results show that the proposed square-root circuit can reduce the area cost by 60%~90% compared with other designs in the literature.

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Section: Implement Results and Comparisonmentioning

confidence: 99%

Section: Implement Results and Comparisonmentioning

confidence: 99%

Section: The Proposed Square-root Algorithmmentioning

confidence: 99%

Section: Proposed Square-root Architecturementioning

confidence: 99%

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A Low-Cost High Radix Floating-Point Square-Root Circuit

2021

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“…Today, the most of implementations of high-performance divider widely use the classic high-radix algorithm in conjunction with a redundant residual representation like carry-save. 13,14 The reason is that high-radix implementations could o®er a superior performance due to the parallelism. However, high-radix implementations require a dedicated hardware, leading to more area cost.…”

Section: Related Workmentioning

confidence: 99%

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

Guo

Cui

et al. 2015

J CIRCUIT SYST COMP

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In this paper, we propose a uni¯ed architecture for computation of double-precision°oatingpoint division, reciprocal, square root, inverse square root and multiplication with a signi¯cant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modi¯ed Goldschmidt algorithm to achieve better area e±ciency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the¯nal accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a recon¯gurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is¯nally implemented and synthesized in SMIC 0.13-m CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area e±ciency (performance/area ratio) of the proposed uni¯ed architecture is increased by about 20% in average, which is a better performance-area trade-o® for embedded microprocessors.

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Novel data dependent divider circuit block implementation for complex division and area critical applications

Patankar

Flores

Koel

2023

Sci Rep

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This article elaborates on the state-of-the-art novel Udayan S. Patankar (USP)-Awadhoot algorithm for distinctive implementation area improvement for area-critical electronic applications. The proposed USP-Awadhoot divider is a digit recurrence class, but it can be flexibly implemented as a restoring or nonrestoring algorithm. The implementation example indicates the use of the Baudhayan-Pythagoras triplet method in association with the proposed USP-Awadhoot divider. The triplet method provides an easy way to generate Mat_Term1, Mat_Term2, and T_Term, which are further utilized with the proposed USP-Awadhoot divider. The USP-Awadhoot divider is implemented in three parts. First is preprocessing circuit stage for executing a dynamic separate scaling operation on input operands, ensuring the inputs are in the correct form. Second is the processing circuit stage for implementing the conversion logic expressed by the Awadhoot matrix, and third is the postprocessing circuit stage for recombining the individual results into the final result. The proposed divider works upto 285 MHz frequency with a power estimation of 3.366 W, also significantly improves the chip area requirements over those of the commercially and noncommercially implemented solutions.

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A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point

Cited by 6 publications

References 10 publications

A Low-Cost High Radix Floating-Point Square-Root Circuit

A Low-Cost High Radix Floating-Point Square-Root Circuit

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

Novel data dependent divider circuit block implementation for complex division and area critical applications

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