A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic

Abdel-Hafeez, Saleh; Gordon‐Ross, Ann

doi:10.1109/tvlsi.2010.2044818

Cited by 22 publications

(18 citation statements)

References 27 publications

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“…Shown as Eq. (5), the logic effort of path G equals the production of each gate's logic effort g. (6) Then, the corresponding gate with the equal input capacitance can be found from the standard logic cells library of the foundry.…”

Section: B Logic Optimizationmentioning

confidence: 99%

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A high-speed and low-power up/down counter in 0.18-μm CMOS technology

Zhang

Hu²

2012

2012 International Conference on Wireless Communications and Signal Processing (WCSP)

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A high speed and power efficient up/down counter is proposed in this paper. Straightforward circuit architecture is adopted for the counter, thus the area and power penalty can be saved. Additionally, several timing optimal methods including logic effort, full-custom methodology for key components and elaborate manual placement and routing are employed to minimize the delay and improve the working frequency. This counter has been fabricated in TSMC 0.18 m CMOS process and the measurement results show that its clock frequency can be up to 1.6GHz and the power dissipation is 7.7mW under 1.8V power supply.

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Section: B Logic Optimizationmentioning

confidence: 99%

“…Recently, Saleh proposed a digital CMOS parallel counter architecture based on state look-ahead logic, in which a pipelined partitioning technology is used [6]. The maximum clock frequency for an 8-bit counter can be up to 2GHz.…”

Section: Introductionmentioning

confidence: 99%

A high-speed and low-power up/down counter in 0.18-μm CMOS technology

Zhang

Hu²

2012

2012 International Conference on Wireless Communications and Signal Processing (WCSP)

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“…For proper working, path delays of counting path and state look-ahead path should be less than the clock period of the counter [1]. Here assuming that access time for both BLK1 and BLK3 are essentially equal.…”

Section: Design Of Clockmentioning

confidence: 99%

“…Mostly these designs have used concept of enabling higher order blocks and ANDing of the overflow states of lower order blocks which have ultimately resulted in increased complexity of design. The designs have poorly performed on counter frequency requirements [1], [2]. These limitations have been guiding force for a better an improved design as proposed in this paper.…”

Section: Introductionmentioning

confidence: 96%

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Design and Simulation of Scalable Fast Parallel Counter

JohnB¹,

R²

2012

IJAIS

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In this research paper, we report an entirely different approach to design a scalable fast parallel counter with improved performance in terms of component and transistor counts. Subsequently the simulation tests are carried out for a wide range of input conditions to validate the design. The main advantages of this scalable counter include low power consumption in milliwatt (mw) range and have speed in the range of GHz. The proposed design is modular in nature indicating that it can easily be upgraded or applied for large counters easily. Repeated use of basic building blocks such as 3-bit synchronous parallel counter, simple D flip flop and 2-bit synchronous parallel counter with enable signal made the design of counter simpler and modular. The logic uses early overflow states enabling all the blocks in the architecture concurrently at the system clock. The pipelined structures together with early overflow based logic provide correct functioning of all building blocks without ripple effects. The design is implemented using Microwind, Digital Schematics (DSCH) and 0.12 µm technologies. Performance shows a total power consumption of 0.164 mw with a clock speed of 1GHz.

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Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Abdel‐hafeez

Gordon‐Ross

2021

Circuit Theory & Apps

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We present a new FIFO (first‐in first‐out) architecture for both synchronous and asynchronous communication for high‐speed and low‐power operation. Our FIFO design is reconfigurable and scalable using a separate datapath with an 8T‐Cell SRAM and control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals such that one signal increments the address pointer, while the other signal activates the memory decoder for data reading and writing. This structure halves the critical path delay and simplifies the timing operations between the memory decoder and address pointer while maintaining robustness against process‐voltage‐temperature (PVT) variations. Our design uses two alternative control circuits to manage separate synchronous and asynchronous operations by generating nonoverlapping control signals that drive the datapath circuit. The empty‐full flag circuitry records only the state of the address pointers' rollover independent of the memory size, and, thus, improves scalability and reconfigurability. Compared to prior works, our design is 5X faster with a 2.3X lower power consumption and has a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle. Additionally, our design functions clocklessly with the synthesizable structure for asynchronous communication that leverages Internet of Things (IoT) and Networks on Chip (NoCs) applications.

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A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic

Cited by 22 publications

References 27 publications

A high-speed and low-power up/down counter in 0.18-μm CMOS technology

A high-speed and low-power up/down counter in 0.18-μm CMOS technology

Design and Simulation of Scalable Fast Parallel Counter

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

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A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic

Cited by 22 publications

References 27 publications

A high-speed and low-power up/down counter in 0.18-&#x03BC;m CMOS technology

A high-speed and low-power up/down counter in 0.18-&#x03BC;m CMOS technology

Design and Simulation of Scalable Fast Parallel Counter

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Contact Info

Product

Resources

About

A high-speed and low-power up/down counter in 0.18-μm CMOS technology

A high-speed and low-power up/down counter in 0.18-μm CMOS technology