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The principal goal of this research work is focused on designing and then testing the performance of source and channel coding and decoding circuits implemented on FPGA for Code Division Multiple Access (CDMA) Transceiver using extremely simple circuit concepts. The paper also describes modulation and demodulation circuits for CDMA. The latest technology advancement in cellular mobile communication systems has become more demanding for better quality of service. It requires broad bandwidth for huge quanta of data transfer. CDMA communication system easily meets these requirements of cellular communications. The design of the relevant circuits is based on CDMA approach of direct sequence spread spectrum technology. The functional performance of designed circuits is tested by carrying out simulations using Field Programmable Gate Arrays (FPGA) and Very High Speed Integrated Circuits Hardware Description Language (VHDL) on XILINX ISE ® and MATLAB ® platforms. The simulated results subsequently have shown quite improved and optimized circuit performance. The performance parameter is mainly based on the number of gates used by CDMA sub-circuits and systems on FPGA implementation.

In this research paper, we report an entirely different approach to design a scalable fast parallel counter with improved performance in terms of component and transistor counts. Subsequently the simulation tests are carried out for a wide range of input conditions to validate the design. The main advantages of this scalable counter include low power consumption in milliwatt (mw) range and have speed in the range of GHz. The proposed design is modular in nature indicating that it can easily be upgraded or applied for large counters easily. Repeated use of basic building blocks such as 3-bit synchronous parallel counter, simple D flip flop and 2-bit synchronous parallel counter with enable signal made the design of counter simpler and modular. The logic uses early overflow states enabling all the blocks in the architecture concurrently at the system clock. The pipelined structures together with early overflow based logic provide correct functioning of all building blocks without ripple effects. The design is implemented using Microwind, Digital Schematics (DSCH) and 0.12 µm technologies. Performance shows a total power consumption of 0.164 mw with a clock speed of 1GHz.