FPGA Implementation of Low Complexity VLSI Architecture for DS-CDMA Communication System

A, Amsavalli; R, Kashwan K.

doi:10.5120/5818-8130

IJCA

2012

DOI: 10.5120/5818-8130

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FPGA Implementation of Low Complexity VLSI Architecture for DS-CDMA Communication System

Amsavalli A¹,

Kashwan K. R²

Abstract: The principal goal of this research work is focused on designing and then testing the performance of source and channel coding and decoding circuits implemented on FPGA for Code Division Multiple Access (CDMA) Transceiver using extremely simple circuit concepts. The paper also describes modulation and demodulation circuits for CDMA. The latest technology advancement in cellular mobile communication systems has become more demanding for better quality of service. It requires broad bandwidth for huge quanta of d… Show more

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Cited by 3 publications

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“…TheXilinx Synthesis Technology (XST) v.12.3 was used for the synthesis of the transmitter. Finley, Amsavalli and Kashwan[70] focused on designing and testing the performance of circuits implemented on FPGA for DS-CDMA transceiver using simple circuit concepts, it describes modulation and demodulation circuits for DS-and MATLAB® platforms. Implementation is carried out on XILINX FPGA chip type xc6vlx75t-3ff484, and simulation is executed using ISE 12.1 version software EDA tool from XILINX.…”

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FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

Nahar¹,

Gitaffa²,

Ali³

et al. 2017

Review of Information Engineering and Applications

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Software Defined Radio (SDR) has the flexibility to modify the characteristics of the receiving and transmitting radio device, without physically adjusting the hardware, due to development in the system. Because of the increasing need for wireless communication applications so as to enable consumers to communicate anywhere through information led to the emergence of many communication devices to include the large amount of applications that every one of the devices needs power and thereby increase the total power. This study confirms that the wireless communication system for secured transmit data, fast and inexpensive; can be done by implementing using Partial Reconfiguration (PR) modern technology in FPGA developing based on SDR. The Speed and performance can be improved. The area also can be decreased. The new Xilinx, Vertex Series FPGA, provides the provision of PR. The power consumption can be reduced by applying power reduction techniques in the blocks. The combination of MATLAB (Simulink and M-file) and Simulink HDL Coder offers flexible capabilities for analysis, design; simulation, implementation, and verification. With all these capabilities, in a single system to reduce the time spent tuning for reducing the algorithms and models during rapid prototyping and experimentation and less time on HDL coding. Contribution/ Originality: This study contributes in the existing literature review for implementing MC-CDMA wireless communication system using Partial Reconfiguration (PR) that is a new technology in FPGA. 1. INTRODUCTION The wireless communications revolution started with the mobile phone at the beginning of the 80's and all the improvements which have led to the multiplication of mobile and wireless communications networks and standards [1]. The 1st Generation (1G) of technology was characterized by analog means voice only; 1G quality was too low and also had connections to low speed, but they effectively offered the inherent easiness of mobile communications. The system used in 1G was Frequency Division Multiple Access (FDMA) [2]. The 2nd Generation (2G) of technology is digital in the United States, most of the devices and services were digital. The spread of digital mobile

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mentioning

confidence: 99%

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

Nahar¹,

Gitaffa²,

Ali³

et al. 2017

Review of Information Engineering and Applications

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Design the MC-CDMA System with LS-PSO Channel Estimation Based FPGA

Nahar¹,

Rahayu²,

Jaber³

2015

RJASET

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The aim of study, providing the best BER performance in channel estimation for Multi Carrier-Code Division Multiple Access (MC-CDMA) system and flexible manner, FPGA design, is using a combination of the SIMULINK family of products, XILINX system generators, XILINX and MATLAB which is suitable for rapid design and verification. In MC-CDMA system, channel estimation is a very important method to work around the influence of channel fading's which jamming pilot symbols and caused BER degradation. That the market for wireless communications infrastructure matures equipment vendors are under increasing pressure to provide low cost solutions for operators and reduce wireless technology complexity. In this study new MC-CDMA channel estimate schema suggested that was based on a combination of Local Search and Particle Swarm Optimization. The proposed channel estimator tested under channel fast fading for different situations. In particular, the transmitter design focus on the 64-QAM system and spreading gold code.

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PAPR Reduction Based on Proposed Rotating Phase Shift Technique in MC-CDMA Using FPGA

Nahar¹,

Gazali²

2015

IJCNS

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FPGA implementation used of Rotating phase shift (RPS) for peak-to-average power ratio (PAPR) reduction in Multi Carrier Code Division Multiple Access (MC-CDMA) signals. Because, MC-CDMA is still suffering from PAPR which is a major drawback in most of the multi carrier communication systems. In addition, the implementation of the system in an FPGA becomes more flexible and scalable. It eliminates the search for optimum phase factors from a given set, which manifests improved PAPR at reduced computational complexity as compared to conventional PTS and SLM. The amplitude of the signal is reduced by rotating each of the partially transmitted sequence anticlockwise by a π/2 degree and the peak power is reduced by circularly shifting the quadrature component of the partially transmitted sequence after phase rotation. A brief description of PTS, SLM is compared with the RPS, which best reduces PAPR from PTS and SLM. It is also presented that VHDL code of the RPS is designed by Xilinx ISE 14.1 implements of FPGA. The peak-to-average power ratio performance of the proposed method has been investigated.

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FPGA Implementation of Low Complexity VLSI Architecture for DS-CDMA Communication System

Cited by 3 publications

References 11 publications

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

FPGA Implementation of MC-CDMA Wireless Communication System Based on SDR-A Review

Design the MC-CDMA System with LS-PSO Channel Estimation Based FPGA

PAPR Reduction Based on Proposed Rotating Phase Shift Technique in MC-CDMA Using FPGA

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