2006
DOI: 10.1109/tcad.2005.855939
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A digital design flow for secure integrated circuits

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Cited by 126 publications
(76 citation statements)
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“…Such approaches follow algorithmic modifications of the cryptography functions realized either in software or in hardware [36]. In the latter case, circuit based modifications can also be made so as to thwart SCAs (e.g., Dual Rail Technology, special CMOS circuits) [43]. The goal of these countermeasures is making the leakage trace of O 1 indistinguishable from the leakage trace of O 0 .…”
Section: Side Channel Analysis Attack Countermeasuresmentioning
confidence: 99%
“…Such approaches follow algorithmic modifications of the cryptography functions realized either in software or in hardware [36]. In the latter case, circuit based modifications can also be made so as to thwart SCAs (e.g., Dual Rail Technology, special CMOS circuits) [43]. The goal of these countermeasures is making the leakage trace of O 1 indistinguishable from the leakage trace of O 0 .…”
Section: Side Channel Analysis Attack Countermeasuresmentioning
confidence: 99%
“…Wave Dynamic Differential Logic (WDDL) is another hardware solution that depends on DDL [37]. Different than scalable hardware architectures [38], the authors in [39] proposed hardware current flattening architecture that used a flatten current feedback module (FCFM) and pipeline current flattening module (PCFM)…”
Section: Side Channel Attacks: Differential Power Analysis Attack (Dpmentioning
confidence: 99%
“…There have been several attacks that exploit weaknesses in caches [5,8,19,21,48,49,50,51,51,52] and branch prediction [6,7,9]. Some countermeasures against these threats include self-destructing keys [32,35,62,72] and new circuit styles that consume the same operational power irrespective of input values [27,38,58,64,65] and microarchitectural techniques [11,22,63,66,69].…”
Section: Related Workmentioning
confidence: 99%