A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

Wang, Ping‐Ying; Zhan, J.-H.C.; Chang, Hsiu-Ju

doi:10.1109/jssc.2009.2022304

Cited by 52 publications

(13 citation statements)

References 13 publications

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“…As the required VCO frequency range increases, larger K VCO is used, therefore a higher resolution DAC is needed to reduce the impact of its quantization noise. In order to reduce the hardware complexity of high resolution DACs [18], [22], DAC architecture is typically employed in DPLLs [1], [23], [24], where a digital modulator with order (p), usually clocked at a higher sampling frequency F DS , drives a single-or a multi-bit DAC (m DAC ) to shape the quantization noise as shown in Fig. 4.…”

Section: A Dual-path Dacmentioning

confidence: 99%

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Elkholy

Saxena

Nandwana

et al. 2016

IEEE J. Solid-State Circuits

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Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoM J ) that quantifies the power-jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0-5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 ps rms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than −96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoM J is −228.5 dB, which is the best among all reported ring-based FNPLLs.

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Section: A Dual-path Dacmentioning

confidence: 99%

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Elkholy

Saxena

Nandwana

et al. 2016

IEEE J. Solid-State Circuits

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“…In this paper, we consider a low-cost TDC-less semidigital PLL architectures [14][15][16][17] which do not require a large integration capacitor in the LPF, achieving technology scalability and leakage current immunity like the ADPLL. Figure 3 shows how the type II PLL obtains frequency acquisition without generating a static phase error.…”

Section: Technology Scalable Semidigital Pllmentioning

confidence: 99%

“…In addition, the phase detector gain can be well regulated over PVT variations if the bias current of the charge pump is generated by an on-chip resistor and a bandgap reference PFD CP voltage [16], which is illustrated in Figure 6. The last one shown in Figure 5(c) uses analog feed-forward circuits (AFFC) to provide a linear phase modulation path [17]. However, having the AC-coupling path at the VCO output requires more complicated design efforts than employing the dual-control path at the VCO input since dealing with high frequency signals is more difficult.…”

Section: δωmentioning

confidence: 99%

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Rhee

Wang

2011

Journal of Electrical and Computer Engineering

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This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

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“…Conversely, built-in self-test (BIST) provides a low-cost solution for pre-shipment screening and manufacturing testing. In addition, the test circuitry can be reused for multiple post-silicon quality assurance tasks including characterization, validation, in-field testing, and postdeployment performance tuning [4].…”

Section: Introductionmentioning

confidence: 99%

An all-digital built-in self-test technique for transfer function characterization of RF PLLs

Wang¹,

Chang

Cheng

2011

2011 Design, Automation &Amp; Test in Europe

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This paper presents an all-digital built-in selftest (BIST) technique for characterizing the error transfer function of RF PLLs. This BIST scheme, with on-chip stimulus synthesis and response analysis completely done in the digital domain, achieves high-accuracy characterization and is applicable to a wide range of PLL architectures. For the popular sigma-delta fractional-N RF PLLs, the added circuitry required for this BIST solution is all digital except a bang-bang phase-frequency detector (BB-PFD), which incurs an area of only 0.0001mm 2 for our implementation in a 65nm CMOS technology. The silicon characterization results at 3.6GHz reported by this BIST solution and by explicit measurement have a root-mean-square difference of 0.375dB only.

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A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

Cited by 52 publications

References 13 publications

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

An all-digital built-in self-test technique for transfer function characterization of RF PLLs

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