A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

Siragusa, E.; Galton, I.

doi:10.1109/jssc.2004.836230

Cited by 181 publications

(53 citation statements)

References 24 publications

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“…By using redundancy bits, the digital error correction technique has been applied to rectify the comparator offset error. But there are some disadvantages with these two techniques like decrease in amplitude of the transmitting, slow convergence speed and deduction of the redundancy space [24][25][26][27]. To overcome these disadvantages, instead of using the pseudorandom noise dither, the variable-amplitude dithering has been used for a digital calibration algorithm for domain-extended pipelined ADCs [10].…”

Section: ) Calibration Using Variable Amplitude Ditheringmentioning

confidence: 99%

On Calibration Techniques for Pipelined ADCs

Narula¹,

Pandey²

2017

IJET

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The development and designing of advanced pipelined analog to digital converter (ADC) is becoming sophisticated day by day as dimensions and supply voltages used for devices are reducing. As the nanometer technology aids fabricating circuits with small footprints, we require high-performance Pipelined ADCs, which are able to rectify analog circuit non-idealities with digital calibration circuits. Digital background calibration is the most favorable solution instead of making changes in analog components in the deep submicron processes. This paper discusses some of the techniques for digital calibration that have been accepted to realize advanced pipelined ADCs. It was observed that on an average, for every two years, the efficiency of ADCs is enhanced by a factor of two. With constant technology scaling supply voltages have reduced and the devices operate at high speed. A closer inspection on SNDR, SFDR, INL and DNL of pipelined ADCs with different calibration techniques is presented here. Finally, a comparison on various design approaches is made to make a view towards additional enhancement in speed, power efficiency and functioning of ADCs.

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Section: ) Calibration Using Variable Amplitude Ditheringmentioning

confidence: 99%

On Calibration Techniques for Pipelined ADCs

Narula¹,

Pandey²

2017

IJET

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“…On top of that, one has to consider that, when matching is concerned, usually multiple elements (N) come in to play, as was clearly shown in the example of section 2.7 (N=192). This stresses the need for techniques that improve matching, like for instance Averaging [42,43], Calibration [56,57], Offset-cancellation [54], Chopping and Dynamic Element Matching [58]. Orders of magnitude improvement in power dissipation can be obtained and sometimes combinations of different techniques can be used.…”

Section: Necessity Of Matching Improvement Techniquesmentioning

confidence: 99%

The Effect of Technology Scaling on Power Dissipation in Analog Circuits

Bult¹

2006

Analog Circuit Design

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A general approach for Power Dissipation estimates in Analog circuits as a function of Technology scaling is introduced. It is shown that as technology progresses to smaller dimensions and lower supply voltages, matching dominated circuits are expected to see a reduction in power dissipation whereas noise dominated circuits will see an increase. These finds are applied to ADC architectures like Flash and Pipeline ADC's and it is shown why Pipeline ADC's survive better on a high, thick-oxide supply voltage whereas Flash ADC's benefit from the technology's thinner oxides. As a result of these calculations an adaptation to the most popular Figure-of-Merit (FOM) for ADC's is proposed.

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“…Among these techniques, correlation-based approaches [4][5][6][7][8][9][10][11][12][13][14][15] are the particular interest as they can obtain an estimation of the ADC errors, with minimum impact on the critical analogue components and low-cost calibration logic, introducing a digital modulation sequence in the stage transfer characteristic (usually a pseudo-random number). These methods perform a full calibration of the amplifier finite DC-gain and capacitor mismatch non-linearity using a single algorithm [4,5]; or considering independent methods for the estimation of both the interstage gain [7][8][9][10][11] and the MDAC non-linear errors [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs

Ginés

Peralías

Rueda

2008

Analog Integr Circ Sig Process

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A novel swapping technique for stage nonlinear error calibration in Pipeline ADCs (analogue-todigital converters) is presented in this paper. The proposed algorithm obtains an estimation of the mismatch between sampling capacitors in the MDAC (multiplying digital-toanalogue converter) inside each stage, without the necessity of interrupting the ADC operation, and therefore, suitable for background calibration applications. The technique also shows its applicability for the amplifier finite DC-gain error, providing a low-cost solution for full calibration of the main static errors in the Pipeline topology with less convergence time, memory resources and simpler calibration hardware than other existing calibration methods. In addition, this work overcomes practical limitations of previous adaptive approaches based on capacitor swapping by introducing a novel modulation scheme. This new scheme minimizes the impact on the analogue part and employs a very simple digital modulation logic.

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A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC

Cited by 181 publications

References 24 publications

On Calibration Techniques for Pipelined ADCs

On Calibration Techniques for Pipelined ADCs

The Effect of Technology Scaling on Power Dissipation in Analog Circuits

New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs

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