“…Thus, effective area of an nmos switch (for say 25k resistor w=2.7um, l=1um) = 2.7um*1um + 0.54um=3.24sq.um. However, in the paper [5] the impedance of the nmos switches is about 0.15ohm, i.e., (high w/l) nmos was considered (hence larger effective area). In addition, the resistor (25k) will consume approximately 35.75um*35.75um chip area in 0.35um CMOS technology [18].…”