Abstract-A monolithic and self-referenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a system-on-chip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phase-locked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low far-from-carrier phase noise to achieve low jitter.

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The quartz crystal (XTAL) oscillator is one of the last components in electronic systems that has yet to be integrated. Consequently, integrating crystal oscillators (XOs) has become a research target for the developers of MEMS microresonators. Recent and representative examples of MEMS oscillators include [1] and [2]. Unfortunately, MEMS microresonators introduce certain challenges including limited power-handling capability [2]. The limitations of MEMS have resulted in recent work, e.g., [3] and [4], exploring the limits of compensated CMOS oscillators as an alternative solution. The advent of RF CMOS circuits and associated advances in CMOS process technology have enabled the development of low-noise integrated LC oscillators (LCOs) [5], which are suitable for replacing XOs in USB applications [3]. This work demonstrates a self-referenced CMOS LCO, or CMOS harmonic oscillator (CHO), that exhibits 90ppm total frequency error over process, bias and temperature, thus making it suitable for replacing XOs in many applications. Additionally, the clock generator can be configured to produce a number of different output frequencies, has 1/4 of the frequency error of the oscillator in [3] and includes a direct modulation technique enabling SSCG. Figure 19.6.1 illustrates the CHO, which exhibits a self-oscillation frequency of 960MHz. A 13b binary-weighted array of MiM capacitors and ring-transistor switches enables the oscillation frequency to be trimmed ±6% with 15ppm resolution. The trimming coefficient is determined during test via an on-chip frequency-locked loop (FLL), in which deep counters for the CHO and a precision reference clock discriminate the frequency error and update the CHO trimming coefficient, as described in [3]. The FLL is controlled by on-chip logic that converges to the optimal trimming coefficient within 100ms by using a binary search algorithm. Additionally, the thin-film capacitor array enables direct modulation of the CHO frequency via a frequency-divided image of itself, thus permitting SSCG without a modulating PLL. The spread rate and depth are controlled digitally by the divide ratio utilized to generate the modulating clock and the capacitor array step size, respectively. The TC of the CHO, which is nearly linear and negative due to the coil loss [3], is compensated via a programmable 6b accumulation-mode MOS (A-MOS) varactor array. When compensation is enabled, the appropriate varactors are connected to a positive linear temperature-dependent voltage, v ctrl (T), and the remaining varactors are connected to the 2.5V power supply. Amplitude control (AC) and common-mode control (CMC) loops minimize frequency drift due to bias variation and device degradation. Long-term frequency drift, or aging, can originate from oxide breakdown and hot carrier mechanisms. Addressing these mechanisms, the AC loop limits the maximum voltage excursion across the passive and active devices, and the CMC loop prevents frequency drift due to device threshold voltage shift induced by hot carriers trapped in th...

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Abstract-A 25MHz all-CMOS clock generator is demonstrated where measured performance makes it suitable for direct replacement of the reference crystal oscillator (XO) for serial wire interfaces. Fabricated in a 0.25μm 1P5M logic CMOS process, and with no external components, the developed clock generator dissipates 59.4mW while exhibiting ±152ppm frequency error over process, ±10% variation in the power supply voltage and from -5-75ºC. Nominal period jitter and power-on start-up latency are 3.93ps rms and 268μs respectively.