A direct bitstream manipulation approach for Virtex4-based evolvable systems

Cancare, Fabio; Santambrogio, Marco D.; Sciuto, D.

doi:10.1109/iscas.2010.5537429

Cited by 29 publications

(28 citation statements)

References 10 publications

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“…Thus, dynamic evolution is used in Evolvable Hardware. Most research during the last 20 years deals with simple digital/analogue circuit synthesis [22], image filtering [16], and system refinements [23]. There is little evidence of real-world applications being implemented, and thus most research is still focussed on refining systems, and testing these refinements by evolving simple circuits such as adders and multipliers [17].…”

Section: Variety Of Researchmentioning

confidence: 99%

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

Smith¹,

Berg²

2015

SACJ

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This paper propose a Virtual-Field Programmable Gate Array (V-FPGA) architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized. By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA); and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm); applying evolution constraints; and optimizing the fitness function. A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness. We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood of an external output being placed in the column decreases. Furthermore, the number of used LEs per column also substantially decreases per added column. Finally, we demonstrated the evolution of a state-decomposed control circuit. It was shown that the evolution of each state’s sub-circuit was possible, and suggest that modular evolution can be a successful tool when dealing with scalability.

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Section: Variety Of Researchmentioning

confidence: 99%

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

Smith¹,

Berg²

2015

SACJ

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“…Upegui and Sanchez used the ICAP to manipulate only the LUT contents (in one dimension) while keeping a fixed routing [14]. Finally, Cancare, Santambrogio and Sciuto extended that concept to two dimensions exploring thus the capabilities of recent Virtex 4 devices [15]. However, only small circuits such as an 8-bit parity generator or 4-bit counter were evolved.…”

Section: Previous Work On Evolvable Systems In Fpgasmentioning

confidence: 99%

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Salvador

Otero

Mora

et al. 2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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This paper addresses the modelling and validation of an evolvable hardware architecture which can be mapped on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The adaptation capabilities of the architecture are exercised to validate its evolvability. The underlying proposal is the use of a library of reconfigurable components characterised by their partial bitstreams, which are used by the Evolutionary Algorithm to find a solution to a given task. Evolution of image noise filters is selected as the proof of concept application. Results show that computation speed of the resulting evolved circuit is higher than with the Virtual Reconfigurable Circuits approach, and this can be exploited on the evolution process by using dynamic reconfiguration.

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“…In arried out directly the LUTs. This iguration speed, ents, reducing the er, the solution is ility is limited to nly 25% of the More recently, a is applied in a [14], with static chieved by means UTs to change its tion channels. A deal with the size Figure 1 shows the system lev proposed System-on-Chip (SoC embedded MicroBlaze processor res the whole system operation, a Rec Core (RC) and a Reconfiguratio modules in the system have been i attached to the Microblaze embed commercial PLB bus that allows the registers of each of the peripherals f…”

Section: Evolvable Hardwarementioning

confidence: 99%

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

Otero

Salvador

Mora

et al. 2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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A direct bitstream manipulation approach for Virtex4-based evolvable systems

Cited by 29 publications

References 10 publications

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

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