A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

Otero, Andrés; Salvador, Rubén; Mora, Javier; Torre, Eduardo de la; Riesgo, Teresa; Sekanina, Lukáš

doi:10.1109/ahs.2011.5963956

Cited by 15 publications

(20 citation statements)

References 13 publications

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“…All arrays need to be evolved in a sequential manner. This situation has been already evaluated in [4].…”

Section: B Evolution Modesmentioning

confidence: 99%

“…The single array evolvable system used as the starting point for this work was presented by the authors in [4].The first part of this section is therefore included to make this paper selfcontained. Transformations performed to make it scalable, being capable to increase or decrease the number of arrays,are shown later.…”

Section: Architecture Of the Evolvable Arraymentioning

confidence: 99%

“…As a trade off solution, authors presented in [4] an architecture, which is a 2-D mesh-type array of fine-grain Processing Elements (PEs), working in a systolic way. Each PE has a specific connectivity and functionality, and it can be selected from a library of presynthesized PBs stored in an external memory.…”

Section: Introductionmentioning

confidence: 99%

“…In order to increase both the adaptability and the selfhealing features of the basic EHW system presented in [4], authors propose in this work the replication of the evolvable array, building an evolutionary structure with a variable number of parallel processing structures arranged in a flexible manner, which includes independent, cascaded, parallel and bypass operation modes. In addition, novel evolutionary strategies and self-healing mechanisms are provided in this work, suited to the proposed architecture.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

Gallego¹,

Mora²,

Otero³

et al. 2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

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“…All arrays need to be evolved in a sequential manner. This situation has been already evaluated in [4].…”

Section: B Evolution Modesmentioning

confidence: 99%

Section: Architecture Of the Evolvable Arraymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

Gallego¹,

Mora²,

Otero³

et al. 2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

Self Cite

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show abstract

“…Combinations of these component states can then be instantiated using partial reconfiguration. The drawback of this approach is that the configuration granularity is relatively coarse, and is thus in the context of EHW mostly suitable for modifying architecture parameters [2], [3] or for evolution of systems using high level functions of a certain complexity [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Lookup table partial reconfiguration for an evolvable hardware classifier system

Glette

Kaufmann

2014

2014 IEEE Congress on Evolutionary Computation (CEC)

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Abstract-The evolvable hardware (EHW) paradigm relies on continuous run-time reconfiguration of hardware. When applied on modern FPGAs, the technically challenging reconfiguration process becomes an issue and can be approached at multiple levels. In related work, virtual reconfigurable circuits (VRC), partial reconfiguration, and lookup table (LUT) reconfiguration approaches have been investigated. In this paper, we show how fine-grained partial reconfiguration of 6-input LUTs of modern Xilinx FPGAs can lead to significantly more efficient resource utilization in an EHW application. Neither manual placement nor any proprietary bitstream manipulation is required in the simplest form of the employed method. We specify the goal architecture in VHDL and read out the locations of the automatically placed LUTs for use in an online reconfiguration setting. This allows for an easy and flexible architecture specification, as well as possible implementation improvements over a hand-placed design. For demonstration, we rely on a hardware signal classifier application. Our results show that the proposed approach can fit a classification circuit 4 times larger than an equivalent VRC-based approach, and 6 times larger than a shift registerbased approach, in a Xilinx Virtex-5 device. To verify the reconfiguration process, a MicroBlaze-based embedded system is implemented, and reconfiguration is carried out via the Xilinx Internal Configuration Access Port (ICAP) and driver software.

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Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration

Salvador

Otero

Mora

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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Adaptive hardware requires some reconfiguration capabilities. FPGAs with native dynamic partial reconfiguration (DPR) support pose a dilemma for system designers: whether to use native DPR or to build a virtual reconfigurable circuit (VRC) on top of the FPGA which allows selecting alternative functions by a multiplexing scheme. This solution allows much faster reconfiguration, but with higher resource overhead. This paper discusses the advantages of both implementations for a 2D image processing matrix. Results show how higher operating frequency is obtained for the matrix using DPR. However, this is compensated in the VRC during evolution due to the comparatively negligible reconfiguration time. Regarding area, the DPR implementation consumes slightly more resources due to the reconfiguration engine, but adds further more capabilities to the system.

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A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems

Abstract: Modern FPGAs with Dynamic and Partial Reconfiguration (DPR)

Cited by 15 publications

References 13 publications

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

Lookup table partial reconfiguration for an evolvable hardware classifier system

Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration

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