A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter

Perraud, L.; Recouly, M.; Pinatel, C.; Sornin, N.; Bonnot, J.-L.; Benoist, F.; Massei, M.; Gibrat, O.

doi:10.1109/jssc.2004.836332

Cited by 36 publications

(22 citation statements)

References 4 publications

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“…A novel architecture using only one frequency synthesizer for dualband conversion is presented. All measured performance meets the requirements of WLAN standards, and consumes less current with superior performance compared to previously published works [3][4].…”

Section: Measured Performancesupporting

confidence: 55%

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A Low-Power Dual-Band WLAN CMOS Receiver

Kao¹,

Kuo²,

Wang³

et al. 2005

2005 IEEE Asian Solid-State Circuits Conference

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A dual-band, dual-conversion receiver integrated from LNA to analog baseband circuitry is presented. The lowpass filters integrate a cutoff frequency auto calibration scheme and can be automatically tuned from 6-MHz to 17-MHz with ±3% accuracy. This design is suitable for multistandard, multi-bandwidth applications, such as 802.11a/b/g and the incoming 802.11n, while the RF front-end is shared. The chip was fabricated in TSMC 0.25um CMOS process with 2.5V power supply. The noise figure is 2.8dB/3.9-dB for 2.4/5-GHz bands at the maximum gain setting, and the iIP3 of 10/-3-dBm is achieved for 2.4/5-GHz bands at the minimum gain. The receiver provides a programmable gain of 88/78-dB in 2dB steps and consumes 51/54-mA current for 2.4/5-GHz bands, respectively.

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Section: Measured Performancesupporting

confidence: 55%

“…This may lead to a low power multi-band multi-standard transceiver solution [3][4]. The frequency planning also provides the advantage of a large separation between the LOs and the RF, avoiding the problem of LO pulling and eliminating the need for imagereject filters.…”

Section: Receiver Architecturementioning

confidence: 99%

A Low-Power Dual-Band WLAN CMOS Receiver

Kao¹,

Kuo²,

Wang³

et al. 2005

2005 IEEE Asian Solid-State Circuits Conference

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“…Many DC offset cancellation (DCOC) methods have been published in the literatures [1][2][3][4][5]. AC coupling [1], a DC feedback loop (DCFL) [2][3][4], and a digital storage system using digital-to-analog converters (DAC) [5] are the most popular DCOC methods.…”

Section: Introductionmentioning

confidence: 99%

“…AC coupling [1], a DC feedback loop (DCFL) [2][3][4], and a digital storage system using digital-to-analog converters (DAC) [5] are the most popular DCOC methods. The AC coupling method requires extremely large capacitors and/or resistors for the large time constant.…”

Section: Introductionmentioning

confidence: 99%

A Transimpedance Amplifier Employing a New DC Offset Cancellation Method for WCDMA/LTE Applications

Lee¹,

Kwon²

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a transimpedance amplifier based on a new DC offset cancellation (DCOC) method is proposed for WCDMA/LTE applications. The proposed method applies a sample and hold mechanism to the conventional DCOC method with a DC feedback loop. It prevents the removal of information around the DC, so it avoids signal-tonoise ratio degradation. It also reduces area and power consumption. It was designed in a 0.13 mm deep n-well CMOS technology and drew a maximum current of 1.58 mA from a 1.2 V supply voltage. It showed a transimpedance gain of 80 dBΩ, an inputreferred noise current lower than 0.9 pA/√Hz, an outof-band input-referred 3rd-order intercept point more than 9.5 dBm, and an output DC offset lower than 10 mV. Its area is 0.46 mm ´ 0.48 mm.

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“…To ease the dynamic range requirements of the analog-to-digital converter (ADC) in the receiving channel, the gain of the receiving path should be adjustable to provide a stable, large-swing output over a span of input signal magnitudes. A receiving signal strength indicator (RSSI) is used extensively in wireless transceivers [1,2] to provide the information necessary to adjust receiver gain. The ability for RSSI circuits to monitor the presence of signals is also useful in power management applications.…”

Section: Introductionmentioning

confidence: 99%

Precise RSSI with High Process Variation Tolerance

Yang

Mason

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-A receiving signal strength indicator (RSSI) built with transconductance amplifiers is presented. The RSSI achieves high tolerance to process variations by utilizing the unique nature of branch currents in a transconductance amplifier. These branch currents are used to implement a current-mode rectifier and amplitude clipping circuit that are tolerant of process variations. An on-chip offset control loop permits the entire RSSI to be realized with only one external component. In 0.18μm CMOS with a 1.8V supply, the RSSI draws 2.5mA and provides 80dB of offset suppression and more than 70dB of log-linear range with less than +/-2dB error due to process variation.

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A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter

Cited by 36 publications

References 4 publications

A Low-Power Dual-Band WLAN CMOS Receiver

A Low-Power Dual-Band WLAN CMOS Receiver

A Transimpedance Amplifier Employing a New DC Offset Cancellation Method for WCDMA/LTE Applications

Precise RSSI with High Process Variation Tolerance

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