A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon–Oxide–Nitride–Oxide–Silicon Device for Reliable Four-Bit/Cell Operations

Abstract

This paper reports the direct observation of the threshold voltage shifts with trapped-charge densities as well as the interface-state densities after 10 4 program/erase (P/E) cycles at each state of the four levels in the drain edge of the silicon-oxide-nitride-oxide-silicon (SONOS) structure. We prepared a SONOS device with a 3.4-nm-thick tunnel oxide, showing 2-bit and 4-level operations at program voltages of 4 -6 V, with a 10-year retention and 10 4 P/E endurance properties. Then, by using charge pumping methods, we observed the vertical and the lateral distributions of the trapped-charges and their interface-states with the gate biases at each level of the four states in the drain edge. The trapped-charges densities at the ''10'', ''01'', and ''00'' states in the drain region were estimated to be 1:4 Â 10 12 , 3:0 Â 10 12 , and 4:9 Â 10 12 cm À2 , respectively, with a lateral width of 220 nm. The peak location of the interface-state density was shifted from the drain edge to the channel with an increase in the gate bias. These observations will be quite useful to optimize the program conditions for reliable 4-bit/cell SONOS operations.

In situ electron holography study of charge distribution in high-κ charge-trapping memory

“…Charge-pumping method 43 is more sensitive to the surface state, so it is employed to find the charges trapped on or close to the interface between SiO 2 and the trap layer 44,45 , but it is difficult to detect the negative charges locating deeply in the HfO 2 layer.…”

Carrier Transport Mechanisms of the Programming and Retention Characteristics for TaN–Al2O3–Si3N4–SiO2–Si Flash Memory Devices

“…[1][2][3][4][5][6][7] The charge trap flash (CTF) memory has emerged as excellent candidates for reducing scale-down problems. [8][9][10][11][12][13] The CTF memory devices utilizing a Si 3 N 4 layer, acting as a charge trap layer, allow a significant improvement in the cell immunity to the stress induced leakage current and the cellto-cell parasitic interference and to enhance the scaling technology perspectives in point of the reliability. [14][15][16][17][18] Because the programming speed of the TaN-Al 2 O 3 -Si 3 N 4 -SiO 2 -Si (TANOS) memory cells with a charge trapping layer increases due to the existence of the Al 2 O 3 layer with a high-k value and a TaN gate with a high work function, the CTF memory devices with a TANOS structure have become particularly interesting for potential applications in next-generation charge trap flash memory cells.…”