A direct-skew-detect synchronous mirror delay for application-specific integrated circuits

Saeki, T.; Minami, K.; Yoshida, Hiroshi; Suzuki, H.

doi:10.1109/4.748189

Cited by 29 publications

(8 citation statements)

References 11 publications

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“…For instance, the closed loop system put forth by Yang and Liu [1], despite of utilizing a binary search algorithm, needs a lock time of at least 20 cycles. On the other hand, open loop locking schemes like the synchronous mirror delay (SMD) require only a few cycles [2]. However, SMD amplifies input jitter and has gate-level resolution.…”

Section: A Hybrid Architecture With Sub-gate Resolutionmentioning

confidence: 99%

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

Kim

Jin

Chun

et al. 2015

2015 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in 65nm CMOS, the proposed DLL occupies 0.0432 mm 2 , and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

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Section: A Hybrid Architecture With Sub-gate Resolutionmentioning

confidence: 99%

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

Kim

Jin

Chun

et al. 2015

2015 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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“…The CSD measures the phase difference between two input clocks using a TDC and compensates the delay of an output clock path. This open-loop scheme achieves a fast lock time [1]. The CSD in the proposed ADDLL is similar to conventional CSD, comprising of a delay line, a multiplexer, and TDC that consists of a delay line, a quantizer, and a 1-to-0 transition detector.…”

Section: Proposed Open-loop Addllmentioning

confidence: 99%

“…This DLL should have a fast lock time for fast wake-up from power-down mode that enables to reduce the system's power consumption. A clock-synchronized-delay (CSD), such as a synchronousmirror-delay (SMD) scheme, achieves fast lock of 2 clock cycles, but suffers from bad resolution that is limited to a unit buffer delay and narrow operating range [1]. To improve the resolution, the residue skew is reduced low by adding a fine delay after coarse locking [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

100MHz-to–1GHz open-loop ADDLL with fast lock-time for mobile applications

Kim

2010

IEEE Custom Integrated Circuits Conference 2010

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This paper presents a fast-lock wide-range all-digital delay locked loops (ADDLL) for mobile applications. The proposed open-loop architecture based on time-to-digital converter (TDC) has a lock time of 3~10 clock cycles. The multipath delay line is implemented to achieve high resolution in TDC. The frequency range selector is adopted for a wide-range operation. The ADDLL is implemented in a 0.18ȝm CMOS process and operates from 100MHz to 1GHz.

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“…For instance, the closed loop system put forth by Yang and Liu [3], despite of utilizing a binary search algorithm, needs a lock time of at least 20 cycles. On the other hand, open loop locking schemes like the synchronous mirror delay (SMD) require only a few cycles [5]. However, SMD amplifies input jitter and has gate-level resolution.…”

Section: Architecturementioning

confidence: 99%

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

Kim¹,

Jin²,

Chun³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NANDdelay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies 0.0432 mm 2 , and consumes 3.7 mW from a 1.2-V supply at 2 GHz.Index Terms-Delay-locked loop, DLL, multi-ditherfree phase detector, fast lock, merged dual delay line, region accumulator

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A direct-skew-detect synchronous mirror delay for application-specific integrated circuits

Cited by 29 publications

References 11 publications

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

100MHz-to–1GHz open-loop ADDLL with fast lock-time for mobile applications

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

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A direct-skew-detect synchronous mirror delay for application-specific integrated circuits

Cited by 29 publications

References 11 publications

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

100MHz-to&#x2013;1GHz open-loop ADDLL with fast lock-time for mobile applications

A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

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Product

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100MHz-to–1GHz open-loop ADDLL with fast lock-time for mobile applications