A Distortion Compensating Flash Analog-to-Digital Conversion Technique

Srinivas, V.; Pavan, Shanthi; Lachhwani, Ashish; Sasidhar, N.

doi:10.1109/jssc.2006.880601

Cited by 25 publications

(7 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They proposed a gray encoded ROM as the solution [12]. In the year 2006, it has been shown that the static nonlinearity presents in the track and hold circuit [13] can be reduced. In 2004, a complementary average value technique was proposed in which the input signal is pre-processed before comparing it with a fixed voltage reference level in order to simplify the comparator design [14].…”

Section: Related Workmentioning

confidence: 99%

A 43μwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180nm CMOS Technology

Kar¹,

Majumder²

2015

IJAST

View full text Add to dashboard Cite

The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are becoming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. Moreover, SoC trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design. Thus, this thesis is to investigate high speed, low power, and low voltage CMOS flash ADCs for SoC applications. In this paper an area efficient low power high Speed 3-bit Flash Type ADC using bit referenced encoder is proposed in 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is also introduced as a modification of the conventional comparator. The proposed design of the ADC occupies an active area of 0.0036 mm2 and consumes 43.146 μW of Average Power while operating with an input frequency (fin) of 10 MHz and a supply voltage of 1.8 Volt.

show abstract

Section: Related Workmentioning

confidence: 99%

A 43μwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180nm CMOS Technology

Kar¹,

Majumder²

2015

IJAST

View full text Add to dashboard Cite

show abstract

“…Sampling and Hold operation [5] can be easily implemented by using simple NMOS transistor with capacitor. Output is measured across capacitor which is connected to Drain terminal.…”

Section: A Bootstrap Switchmentioning

confidence: 99%

A distortion compensating flash Analog-to-Digital conversion using bootstrap switch

T.P

HarshaVardhan

Ramesh

2014

2014 International Conference on Advances in Electrical Engineering (ICAEE)

View full text Add to dashboard Cite

This paper proposes Flash Analog to Digital Converter design that reduces static nonlinearity of the track & hold circuit, by that high speed and high linearity obtained at the same time. Comparator is designed using latch type voltage sense amplifier. The sense amplifier is designed with separated input and regeneration stage. This separation offers fast operation over a wide common mode and supply voltage range. Apart from sense amplifier this Analog to Digital converter design uses Thermometer code generator circuit followed by encoder. The input is sampled and held by (S/H) circuit so that there is no need to use bubble correction logic in the design.

show abstract

“…They propose a gray encoded ROM as the solution. In the year 2006, it has been shown that the static nonlinearity presents in the track and hold circuit [9] can be reduced. In 2004, a complementary average value technique has been proposed in which the input signal is pre-processed before comparing it with a fixed voltage reference level in order to simplify the comparator design [10].…”

Section: Related Earlier Workmentioning

confidence: 99%

Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications

Dutta¹

2013

IOSR-JECE

View full text Add to dashboard Cite

In modern era of advanced VLSI design the transistor sizing and scaling has an considerable impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital data converter (ADC) in 45nm CMOS technology is presented for low power and high speed system-on-chip (SoC) applications. This low power 8-bit flash Analog to Digital data converter comprises 255 comparators and one thermometer to binary encoder. This flash ADC design is an extended research work of the earlier work related to ADC design using CMOS process technology. The schematic simulation of ADC is done in Tanner-Spice Pro (S-Edit) and layout simulation is done in Tanner-Spice Pro (L-Edit) V.15.14. The Simulated result shows the power consumption in Flash ADC is 41.78μw. The Threshold Inverter Quantization (TIQ) technique is proposed to get WPMOS/WNMOS < 1 for transistors to keep the power consumption as low as possible. It is also observed that the ADC consumes 41.78μW of peak power and 6.45μW of average power at full speed while it operates on a power supply voltage of 0.6V. Compared with the earlier work, this project consumes less power and high speed with proposed TIQ technique gives an edge in SoC based VLSI design. Finally the Signal to Noise Distortion analysis is done to obtain more precise data conversion results. The SNDR was found 31.9dB for ultimate precise data conversion using 45nm CMOS process technology.

show abstract

A Distortion Compensating Flash Analog-to-Digital Conversion Technique

Cited by 25 publications

References 11 publications

A 43μwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180nm CMOS Technology

A 43μwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180nm CMOS Technology

A distortion compensating flash Analog-to-Digital conversion using bootstrap switch

Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications

Contact Info

Product

Resources

About