A distributed architecture to check global properties for post-silicon debug

Larsson, Erik; Vermeulen, Bart; Goossens, Kees

doi:10.1109/etsym.2010.5512760

Cited by 8 publications

(2 citation statements)

References 10 publications

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“…Larsson et al [44] describe on‐chip monitor hardware which is capable of detecting the occurrence of an incorrect read/write sequence, because of the presence of a race condition, when two CPUs access shared memories. The monitor described involves a bus interface, address/data matching circuits and a state machine, which can be reprogrammed in‐circuit to monitor different potential race conditions.…”

Section: Runtime Monitorsmentioning

confidence: 99%

On‐chip support for software verification and debug in multi‐core embedded systems

2013

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The challenges in silicon testing and debug of complex integrated circuits are well understood. Where these circuits include multiple processor cores there is also a dramatic increase in the complexity of verifying and debugging the associated software; with much of this complexity being because of the inherent lack of visibility over internal signals which integration brings. The trend to-date has been to rely upon silicon test interfaces to provide access to internal signals required for software verification and debug. However, it is questionable whether this is sufficient for real-time systems or future designs with increasing processor cores. This study examines the on-chip technology supporting software verification and debug in current designs and proposes enhancements in this area. As much of this technology is primarily intended for silicon test it is lacking in terms of I/O bandwidth, which is a significant limitation for software verification and debug. The authors propose their alternative approach of using an on-chip coprocessor and debug circuitry to address this principal limitation; and describe an embedded application where this approach was successfully applied to monitor timing requirements and detect failures. The authors also outline how this approach could be applied as an architectural solution for formal runtime verification.

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Section: Runtime Monitorsmentioning

confidence: 99%

On‐chip support for software verification and debug in multi‐core embedded systems

2013

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“…If both the data and the remote administration are in the same memory the ordering of data and synchronisation transaction is guaranteed. This is, however, not the case when data and synchronisation have different QoS budgets in the interconnect [35]. For this purpose we include an ARM Data Memory Barrier (DMB) operation in the release call, or a read back of the last written value for processors without such functionality.…”

Section: Buffer Management and Task Executionmentioning

confidence: 99%

Design and implementation of an operating system for composable processor sharing

Hansson

Ekerhult

Molnos

et al. 2011

Microprocessors and Microsystems

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a b s t r a c tMulti-Processor Systems on Chip (MPSoC) run multiple independent applications, often developed by different parties. The applications share the hardware resources, e.g. processors, memories and interconnect. The sharing typically causes interference between the applications, which severely complicates system integration and verification. Even if the applications are verified in isolation, the system designer must verify the combined behaviour, leading to an explosion in design complexity. Composable MPSoCs have no interference between applications, thus allowing independent design and verification. For an MPSoC to be composable, all the hardware resources must offer composability. A particularly challenging resource is the processors, often purchased as off-the-shelf intellectual property.In this work we present the design and implementation of CompOSe, a light-weight (only 1500 lines of code) composable operating system for MPSoCs. CompOSe uses fixed-size time slices, coupled with a composable scheduler, to enable composable processor sharing. Using instances of ARM7, ARM11 and the Xilinx MicroBlaze we experimentally demonstrate the ability to provide temporal composability, even in the presence of dynamic application behaviour and multiple use cases. We do so using a diverse set of processor architectures, without requiring any hardware modifications. We also show how CompOSe allows slack to be distributed within and between applications through a novel two-level scheduler and slack-distribution system.

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Post-silicon Debugging of Multiple Building Blocks

Vermeulen

Goossens

2014

Embedded Systems

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A distributed architecture to check global properties for post-silicon debug

Cited by 8 publications

References 10 publications

On‐chip support for software verification and debug in multi‐core embedded systems

On‐chip support for software verification and debug in multi‐core embedded systems

Design and implementation of an operating system for composable processor sharing

Post-silicon Debugging of Multiple Building Blocks

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