In this article we present test and verification challenges for system chips that utilise on-chip networks. These systems on a chip (SOCs) and networks on a chip (NOCs) are introduced, where the NOC is exemplified by Philips's AETHEREAL NOC architecture. We discuss existing test and verification methods for SOCs and NOCs, and show the particular advantages of using a NOC both for testing and verifying the network, and for testing and verifying the other components of the SOC. This paper is concluded with our experiences with NOCs and a description of on-going work within Philips in this emerging field.

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I For today's multi-million transistor designs, existing design verijication techniques cannot guarantee that first silicon 1 is designed error free. Therefore, techniques ate necessary to eflciently debug firstsilicon. In this article, we present a methodology for debugging multiple clock domain systems-on-a-chip. In addition to scan chains, a set of Design-for-Debug modules is 1 designed into an IC to make it debuggable. bebugger tool sofhvare interacts with the on-chip DjD to make the debug features available from a workstation.

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