Core-based scan architecture for silicon debug

Vermeulen, Bart; Waayers, Tom; Goel, Sandeep

doi:10.1109/test.2002.1041815

Cited by 59 publications

(36 citation statements)

References 15 publications

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“…4(a), some important vectors or representing vectors can be used for fault simulation and error transmission matrix generation. Commonly, since random instructions are run to exercise various part of a chip [6], [18], [19], some random instructions could be a good choice for sample vector based approach.…”

Section: Techniques To Generate Error Transmission Matrixmentioning

confidence: 99%

“…Scan chains are widely utilized to support manufacturing test as a design-for-testability feature. Scanbased debug techniques [9], [18], [19] significantly enhance the internal signal observability, however, the system needs to be halted to read out responses from the circuit-under-debug. A trace buffer is an on-chip memory that can store the continuous internal signal information for a limited time period.…”

Section: Introduction and Related Workmentioning

confidence: 99%

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Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

Yang

Touba

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Techniques To Generate Error Transmission Matrixmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis

Yang

Touba

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Scan chains are inserted during Design-for-Test and they are later reused in silicon debug [21]. They work by connecting all scanned registers in a large shift register.…”

Section: A Design For Silicon Debug Techniquesmentioning

confidence: 99%

From RTL to silicon: The case for automated debug

Veneris

Keng

Safarpour

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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Abstract-Computer-aided design tools are continuously improving their scalability and efficiency to mitigate the high cost associated with designing and fabricating modern VLSI systems. A key step in the design process is the root-cause analysis of detected errors. Debugging may take months to close, introduce high cost and uncertainty ultimately jeopardizing the chip release date. This study makes the case for debug automation in each part of the design flow (RTL to silicon) to bridge the gap. Contemporary research, challenges and future directions motivate for the urgent need in automation to relieve the pain from this highly manual task.

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“…We reuse the scan chains that embedded systems use for manufacturing test to create access to all state in the chip's flipflops and memories via the TAP. 11 This helps minimize silicon area cost.…”

Section: Scan-based Debugmentioning

confidence: 99%