Test and debug strategy of the PNX8525 Nexperia/sup TM/ digital video platform system chip

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

“…In this paper, logic blocks belonging to different clock domains are grouped as different virtual cores (VCs). For each VC, a single-frequency virtual wrapper, 1 containing the WSCs for the respective group, is assigned. In addition, the switching between shift clock signal and capture clock signal is conducted with glitch-free multiplexors (advanced techniques such as [18] is not necessary because we only need to switch between two clock signals).…”

“…The virtual wrapper is connected to the core interface through internal virtual test bus (VTB) lines. To tradeoff the TAT against test power, the number of internal VTB lines (W vtb ) is not necessarily the same as the external test access mechanism (TAM) 1 The final wrapper design is still at the core-level, and the virtual core concept is proposed mainly as a stepping stone for better understanding. width assigned to the core (W ext ).…”

“…We can easily observe the difference between the scan shift frequencies and phases. The frequency of Gated_clk [3] is half of the frequencies of Gated_clk [1] and Gated_clk [2] in Fig. 3(b).…”

“…Modern system-on-a-chip (SOC) uses embedded cores that operate internally with multiple clock domains (e.g., [1]). In addition, some cores may operate internally at very high rates, typically employing phase-locked loops (PLL) to generate on-chip clocks from far slower external reference signals.…”

Wrapper design for testing IP cores with multiple clock domains

“…In addition, many embedded cores operate internally using multiple frequencies. For example, for the design reported in [11] all the cores have more than three clock domains. To illustrate a multiple-frequency core-based SOC, Figure 1 shows a simple hypothetical design that comprises three cores with three different physical clocks.…”