A Distributed Bulk-Oxide Trap Model for $\hbox{Al}_{2} \hbox{O}_{3}$ InGaAs MOS Devices

InAlAs has the potential to be used as a barrier layer in buried channel quantum well field effect transistor devices due to favorable lattice-matching and carrier confinement properties with InGaAs. Field effect device structures of this nature may also require a high-k oxide deposited on the InAlAs surface to reduce leakage current. This study investigates the impact of surface preparations and atomic layer deposition of HfO2 on these surfaces using x-ray photoelectron spectroscopy to analyse the chemical interactions taking place, as well as the electrical performance of associated capacitor devices. A large concentration of As related surface features is observed at the InAlAs surface, and is attributed to a large D-it response in electrical measurements. (C) 2013 AIP Publishing LLC

Section: Resultsmentioning

confidence: 99%

Chemical and electrical characterization of the HfO2/InAlAs interface

Brennan

Galatage

Thomas

et al. 2013

“…A distance (x) for the spatial location of the border traps relative to the In 0.53 Ga 0.47 As interface can be estimated using the relationship 33 x ¼ k lnðt=sÞ; (7) where k is the attenuation coefficient and t is the tunnelling time. Assuming a k value within the typical range of 9.8 Â 10 À9 -1.25 Â 10 À8 cm reported for the Al 2 O 3 / In 0.53 Ga 0.47 As interface [16][17][18]21,30 and considering that N CP saturation is reached at t $ 5 ls (Fig. 6), we obtain a distance x of about 1.6-2.1 Å from the interface.…”

Section: Transient Charging Time and Border Trap Responsementioning

confidence: 71%

“…Recent studies have indicated the presence of border traps in high-k/InGaAs MOS structures using C-V, [15][16][17][18][19] charge pumping 20 and high-frequency transconductance 21 measurements. Evidence of the presence of border traps can also be observed in an I d -V g characteristic, where it is manifest as a hysteresis loop.…”

Section: B Evidence Of Border Trap Responsementioning

confidence: 99%

“…This range of values is in agreement with other studies of border traps in the high-k/InGaAs system. 18,21,34 It is noted that the discussion of the D bt ÁDt bt ÁDE data relies on the energy vs gate bias and trap density vs energy profiles obtained from a previous C-V study that we performed on the same set of devices as that used in this study. 27 Moreover, since Dt bt cannot be obtained from our ICP-based approach, a value of $ 2 Å is assumed from Ref.…”

Section: Transient Charging Time and Border Trap Responsementioning

confidence: 99%

See 1 more Smart Citation

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

Djara

Cherkaoui

Negara

et al. 2015

Original citationDjara, V., Cherkaoui, K., Negara, M. A. and Hurley, P. K. (2015) An alternative multi-frequency inversion-charge pumping (MFICP) technique was developed to directly separate the inversion charge density (N inv ) from the trapped charge density in high-k/ InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). This approach relies on the fitting of the frequency response of border traps, obtained from inversion-charge pumping measurements performed over a wide range of frequencies at room temperature on a single MOSFET, using a modified charge trapping model. The obtained model yielded the capture time constant and density of border traps located at energy levels aligned with the InGaAs conduction band. Moreover, the combination of MFICP and pulsed I d -V g measurements enabled an accurate effective mobility vs N inv extraction and analysis. The data obtained using the MFICP approach are consistent with the most recent reports on high-k/InGaAs. V C 2015 AIP Publishing LLC.

“…17,18 Since trap states inside the gate insulator, called border traps, do have long time constants as they interact with the conduction band electrons, 10 some authors have proposed that these oxide traps are responsible for the frequency dispersion. [19][20][21][22][23] As the surface potential moves into the lower half of the band-gap, the semiconductor minority carriers start to interact with interface states. 20,24 Therefore, the effect of border traps weakens, and the frequency dispersion of the capacitance in the inversion region can be attributed to the interface traps inside the band-gap taking over the dominant role.…”

Section: Resultsmentioning

confidence: 99%

Investigation of stress induced interface states in Al2O3/InGaAs metal-oxide-semiconductor capacitors

Palumbo

Winter

Tang

et al. 2017

Implementation of high-k dielectrics on InGaAs for CMOS technology requires capabilities to predict long-time degradation and the impact of process changes on degradation processes. In this work, the degradation under constant voltage stress of metal gate/Al 2 O 3 /InGaAs stacks is studied for n-type and p-type As 2 passivated InGaAs substrates. The results show that the degradation for both positive bias and negative bias did not produce Al 2 O 3 oxide traps, while the distribution of interface states increased. In particular, the distribution of interface states, calculated by the distributed impedance equivalent circuit model, increased significantly after positive bias stress regardless of the doping type of the substrate. The injection of carriers from the semiconductor conduction band into the gate dielectric enhanced the generation of interface states but not the generation of oxide traps, suggesting that the interfacial degradation is related primarily to the InGaAs surface and not to the oxide layer. Published by AIP Publishing.