Investigation of stress induced interface states in Al2O3/InGaAs metal-oxide-semiconductor capacitors

Abstract

Implementation of high-k dielectrics on InGaAs for CMOS technology requires capabilities to predict long-time degradation and the impact of process changes on degradation processes. In this work, the degradation under constant voltage stress of metal gate/Al 2 O 3 /InGaAs stacks is studied for n-type and p-type As 2 passivated InGaAs substrates. The results show that the degradation for both positive bias and negative bias did not produce Al 2 O 3 oxide traps, while the distribution of interface states increased. In particular, the distribution of interface states, calculated by the distributed impedance equivalent circuit model, increased significantly after positive bias stress regardless of the doping type of the substrate. The injection of carriers from the semiconductor conduction band into the gate dielectric enhanced the generation of interface states but not the generation of oxide traps, suggesting that the interfacial degradation is related primarily to the InGaAs surface and not to the oxide layer. Published by AIP Publishing.

Trap Characterization of Atomic-Layer-Deposited Al-Incorporated HfO2 Films on In0.53Ga0.47As

“…The positive shift of the threshold voltage at a positive bias stress indicates electron trapping from the semiconductor to the oxide and passivation of positive charge. 53 From the figure, it is observed that sample A [3:3] has the lowest shift of 86.2 mV while sample D [1:9] has the highest (282.5 eV). Thus, this stress-induced charge trapping maintains a linearity with the Hf content with a higher amount of Hf causing a higher quantity of charges to be trapped.…”

“…The threshold voltage shift (Δ V TH ) after 2000 s of CVS at 1.5 V for all samples is illustrated in Figure c, where Δ V TH is the difference of the threshold voltage of a fresh device and stressed device. The positive shift of the threshold voltage at a positive bias stress indicates electron trapping from the semiconductor to the oxide and passivation of positive charge . From the figure, it is observed that sample A [3:3] has the lowest shift of 86.2 mV while sample D [1:9] has the highest (282.5 eV).…”