A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter

Takinami, Koji; Strandberg, Roland; Liang, Paul; Mercey, G. Le Grand de; Wong, Tony; Hassibi, Mahnaz

doi:10.1109/jssc.2011.2164011

Cited by 24 publications

(19 citation statements)

References 28 publications

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“…20 in which the largest spur level is at 470 kHz offset and the closest spur is 230 kHz (470 kHz/2). The sub harmonic and harmonic spurs can be originated from a DCO quantization, a TDC quantization, an intermodulation related to the amount of inherent jitter, and a parasitic coupling of CKR-controlled switching in many digital gates sharing the same substrate, power and ground planes with DCO [5], [8], [20], [21]. The ADPLL phase noise curves measured using Agilent E5052B signal source analyzer are plotted like in Fig.…”

Section: Whenmentioning

confidence: 99%

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A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

Lee

Park

Min

et al. 2012

IEEE Trans. Circuits Syst. I

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This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves in-band phase noise, integrated noise, and 740 ns settling time.

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Section: Whenmentioning

confidence: 99%

“…22. The effective TDC resolution of (11) can be derived from the measured in-band phase noise [5], [19].…”

Section: Whenmentioning

confidence: 99%

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

Lee

Park

Min

et al. 2012

IEEE Trans. Circuits Syst. I

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“…However, in practice, quantization errors introduced by the fractional divider (FDIV), TDC, and DAC degrade digital FNPLL performance. As a result, jitter performance of digital FNPLLs, especially those using ring oscillators, is grossly inferior to their analog counterparts [1], [8]- [12]. Ring oscillators are extremely low-cost, scalable, and can inherently provide multiple phases with a wide tuning range.…”

mentioning

confidence: 99%

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Elkholy

Saxena

Nandwana

et al. 2016

IEEE J. Solid-State Circuits

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Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoM J ) that quantifies the power-jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0-5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 ps rms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than −96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoM J is −228.5 dB, which is the best among all reported ring-based FNPLLs.

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“…The closed-loop transfer function of the system takes the general form shown in The all-digital implementation of the PLL is advantageous because it allows the system to be more easily integrated with other digital components on an IC by eliminating the need for analog subsystems such as the charge pump and the RC loop filter which may require off-chip resistors and capacitors [3], [14]. Since this is now a digital system, a reference clock signal is required for synchronously clocking the digital components.…”

Section: Conventional Analog Pllmentioning

confidence: 99%

“…A DCO uses an array of digital inputs to control a bank of binary-and unit-weighted switchable capacitors, or varactors, of varying sizes [2], [14], [15], [16]. Because of the digital nature of the tuning varactor bank, the DCO has a finite minimum step size determined by the size of the smallest varactors.…”

Section: Conventional Analog Pllmentioning

confidence: 99%

A Rotary Travelling Wave Oscillator Based All-Digital PLL in 65nm CMOS

Cathcart¹

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This thesis presents the design and implementation of an All-Digital Phase Locked Loop (ADPLL) that uses Delta-Sigma (ΔΣ) modulation, multi-phase outputs, and Dynamic Element Matching (DEM). The system is designed using a combination of 65nm CMOS technology and an FPGA. The frequency range of the ADPLL output is 5.48GHz to 6.22GHz. Several design techniques are used to reduce the phase noise of the ADPLL output. The ADPLL uses a rotary travelling wave-based Digitally Controlled Oscillator (DCO) with multi-phase outputs to improve quantization noise. Manufacturing variations on the fine-tuning DCO input capacitors are averaged using DEM to produce more uniform frequency steps. ΔΣ modulation is used on the least significant of the DCO input bits. This modulation introduces a dithering effect on the output frequency that has the effect of moving some of the phase noise away from the ADPLL carrier frequency.

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A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter

Cited by 24 publications

References 28 publications

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation

A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

A Rotary Travelling Wave Oscillator Based All-Digital PLL in 65nm CMOS

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