A distributed-RCL model for MCM layout

Zhou, Dian; Tsui, Frank; Cong, Jason; Gao, Di

doi:10.1109/mcmc.1993.302128

Cited by 13 publications

(9 citation statements)

References 10 publications

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“…Traditionally, treel is considered as the optimal implementation which provides the minimal delay under the lumped RC model. However, using the distributed RLC model and the two-pole approximation established in the previous section we can construct an A-tree (tree2) which gives a shorter delay and smaller overshooting than that the minimum Steiner tree dose, as demonstrated in figure 8 [9]. In other words, tree2 provides a better performance as compared with treel.…”

Section: Waveform Delay and Design Examplementioning

confidence: 98%

A Simplified Synthesis of Transmission Lines with a Tree Structure

Zhou¹,

Su²,

Tsui³

et al. 1994

Modeling and Simulation of High Speed VLSI Interconnects

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Abstract. The limiting factor for high-performance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a generic distributed RLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform and delay in an RLC tree. The result on the RLC tree is then extended to the case of a tree consisting of transmission lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.

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Section: Waveform Delay and Design Examplementioning

confidence: 98%

A Simplified Synthesis of Transmission Lines with a Tree Structure

Zhou¹,

Su²,

Tsui³

et al. 1994

Modeling and Simulation of High Speed VLSI Interconnects

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“…The delay 1.0 the critical sink(s) and the total wiring area of the different wiresizing solutions are compared. T h e signal delay is computed using the two-pole circuit simulator developed by Zhou et al [16]. Extensive experimenkal results have shown that the two-pole simulator is comparable t o SPICE in delay simulation, but runs much faster 1161.…”

Section: Comparisons Between Different Wiresiz-mentioning

confidence: 99%

Optimal wiresizing under the distributed Elmore delay model

Cong¹,

Leung²

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

111

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In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interestingproperties, including the separability, the monotone property, and the dominance property. Based on these properties, we develop a polynomial-time optimal wiresizing algorithm for arbitrary interconnect structures under the distributed Elmore delay model. Extensive experimental results show that our wiresizing solution reduces interconnection delay by up to 5i% when compared to the uniform-width solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model in [7], our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnection delays to the timing-critical sinks by up to 12%.

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“…Since the admittance and voltage at the far end of the lines are known from (19), (20) and (21) can be determined using the distributed-parameter REX. The first-and second-order coefficients of the voltages at the other end of the lines is given by using (17) and (18).…”

Section: Zero-skew Clock-tree Construction For Rlc Linesmentioning

confidence: 99%

“…It is important to control ringing in the clocking network because this could lead to undesirable cross talk, and because high overshoots/undershoots could also cause devices to switch incorrectly. However, we consider the possibility of allowing a small overshoot of controlled magnitude, as this can ensure an improved signal slew rate [1], [10], [19]. The specific contributions of this work are the use of a higher order moment matching to reduce the skew, the design of the clock tree with controlled damping criterion to ensure signal integrity while improving the timing performance, and a strategy for the use of buffered clock trees in the MCM scenario.…”

mentioning

confidence: 99%

Moment-based techniques for RLC clock tree construction

Lehther

Sapatnekar²

1998

IEEE Trans. Circuits Syst. II

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While designing interconnect for MCM's, one must take into consideration the distributed RLC effects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCM's. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for buffer insertion to satisfy constraints on the clock signal slew rate. Experimental results, verified by SPICE simulations, show that this method can be used to build clock trees with near-zero skews. Computational efficiency along with its accuracy make this method ideal for computer-aided design (CAD) of RLC clock trees.

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A distributed-RCL model for MCM layout

Cited by 13 publications

References 10 publications

A Simplified Synthesis of Transmission Lines with a Tree Structure

A Simplified Synthesis of Transmission Lines with a Tree Structure

Optimal wiresizing under the distributed Elmore delay model

Moment-based techniques for RLC clock tree construction

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