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The paper presents a new method to synthesize macromodels for very large on-chip interconnection networks which can be simulated very efficiently with traditional SPICE-like simulators. The method is taking advantage of the fact that in CMOS VLSI circuits, the receiving ports of the dock distribution network can be accurately modeled by lumped passive impedances. Our method simplifies the task of simulating the interconnect by building a reduced order macromodel only for the subset of driving ports of the net. The signals at the passive ports can be determined, in a later stage, as linear combinations of a reduced set of primary signals, obtained during the simulation of the driving ports macromodel. The simulation time for the macromodels generated in this way is greatly reduced, the size of the macromodels is kept small and the accuracy is preserved.