No abstract

Recenily, seveml design auiomaiion approaches for delay and skew minimization of clock nets have been proposed. These approaches are based upon varying the widths and lengths of the clock tree wires io minimize skew and sometimes delay. Most of these iechniques do noi consider the clock iree power dissipation, occupied area, or the reliabiliiy of ihe resvlts with regard to the ineviiable process variations. In this paper, concurreni buffer insertion and global wire width adjusimenis are used to reliably reduce both delay and power from that obtained for a reliable buflerless soluiion. Moreover, in spite of ihe belief ihai ihe mismaich in bufler delays can resuli in significant clock skew, our resulis show ihai buflers can actually reduce the process dependent skew for a reliable design.

No abstract

An approach for accurately modeling the RC-interconnect delay and gate-loading effects in a hierarchical timing analyzer is presented. The change in gate-loading due to interconnect resistance is considered by an "effective capacitance" approximation. The RC-interconnect path delays are precharacterized in terms of an interpolating polynomial function.

No abstract