No abstract

An approach for accurately modeling the RC-interconnect delay and gate-loading effects in a hierarchical timing analyzer is presented. The change in gate-loading due to interconnect resistance is considered by an "effective capacitance" approximation. The RC-interconnect path delays are precharacterized in terms of an interpolating polynomial function.

This paper describes RICE, an RLC interconnect evaluation tool based upon the moment-matching teehnique of Asymptotic Waveform Evaluation (AWE). The RLC circuit moments are calculated by a path-tracing algorithm which enables the analysis of large interconnect models several thousand times faster than a circuit simulation while requiring 5 to 10 times less memory. RICE also includes anew approach for determining the circuit dominant time-constants which avoids the inherent instability problems associated with moment matching methods in geneml.AWE permits the analysis of interconnect models other than RC-trees and therefore coupling capacitance, resistor loops, and inductance rue handled without loss of generality. Such 28th ACM/l EEE Design Automation Conference" Paper 33,1 555 01991 ACM 0-89791-395-7/91/0006/0555 $1.50