For digital system designs the propagation delays due to the physical interconnect can have a significant, even dominant, impact on performance. Timing analyzers attempt to capture the effect of the interconnect on the delay with a simplified model, typically an RC tree. For mid-frequency MOS integrated circuits the RC tree methods can predict the delay to within 10 percent of a SPICE simulation and at faster than lOOOx the speed. With continual progress in integrated circuit processing, operating speeds and new technologies are emerging that may require more elaborate interconnect models. Digital bipolar and high-speed MOS integrated systems can require interconnect models which contain coupling capacitors and inductors. In addition, to enable timing verification at the printed circuit hoard level also requires general RLC interconnect models. Asymptotic Waveform Evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations. The RLC interconnect model may contain floating capacitors, grounded resistors, inductors, and even linear controlled sources. The transient portion of the response is approximated by matching the initial boundary conditions and the first 2q-1 moments of the exact response to a lower order q-pole model. For the case of an RC tree model a first-order AWE approximation reduces to the RC tree methods.

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--As signal speeds increase and gate delays decrease for high-perform ance digital integrated circuits, the gate delay m odeling problem becom es increasingly m ore difficult. With scaling, increasing interconnect resistances and decreasing gateoutput im pedances m ake it m ore difficult to em pirically characteriz e gate-delay m odels. Moreover, the single-input-switching assum ption for the em pirical m odels is incom patible with the inevitable sim ultaneous switching for todays high-speed logic paths.In this paper a new em pirical gate delay m odel is proposed.Instead of building the em pirical equations in term s of capacitance loading and input-signal transition tim e, the m odels are generated in term s of param eters which com bine the benefits of em pirically derived k -factor m odels and switch-resistor m odels to efficiently: 1) handle capacitance shielding due to m etal interconnect resistance, 2) m odel the RC interconnect delay, and 3) provide tighter bounds for sim ultaneous switching.