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--As signal speeds increase and gate delays decrease for high-perform ance digital integrated circuits, the gate delay m odeling problem becom es increasingly m ore difficult. With scaling, increasing interconnect resistances and decreasing gateoutput im pedances m ake it m ore difficult to em pirically characteriz e gate-delay m odels. Moreover, the single-input-switching assum ption for the em pirical m odels is incom patible with the inevitable sim ultaneous switching for todays high-speed logic paths.In this paper a new em pirical gate delay m odel is proposed.Instead of building the em pirical equations in term s of capacitance loading and input-signal transition tim e, the m odels are generated in term s of param eters which com bine the benefits of em pirically derived k -factor m odels and switch-resistor m odels to efficiently: 1) handle capacitance shielding due to m etal interconnect resistance, 2) m odel the RC interconnect delay, and 3) provide tighter bounds for sim ultaneous switching.

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In this paper we develop a gate level model that allows us to determine the best and worst case delay when there is dominant interconnect coupling. Assuming that the gate input windows of transition are known, the model can predict the worst and best case noise, as well as the worst and best case impact on delay. This is done in terms of a Ceff based gate model under general RC interconnect loading conditions. [ ] ∈