AbstiactIncreases in delay due to coupling can have a dramatic impact on IC pe~ormance for deep submicron technologies. To achieve marimum pe~ormance there is a needfor analyziltg logic stages with large complex coupled interconnects. In timirtg analysis, the worst-case delay of gates along a critical path must include the eflect of noise due to switching of nearby aggressor gates. In this papec we propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align agsressor inputs to determine the worst-case victim delay. We demonstrate the application of our methodology at both the transtitor-level and celllevel. IIt addition, we prove that the waveforms generated in our methodology converge under typical timing a~lysis conditions.

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Crosstalk between adjacent lines can affect the propagation delay of signals in Deep-Submicron (DSM) circuits. When such a circuit is subjected to conventional delay testing techniques, the critical paths obtained from static timing analysis are incorrect due to the effect of crosstalk.can have many wires (victims)which are affected by crosstalk many other lines (aggressors).It may so happen that all the wires lying along a path are affected by crosstalk and the cumulative effect of crosstalk delays of all these victim nodes causes a timing violation. In such a case, all the aggressors associated with the victims lying along the path need to be activated appropriately in order to maximize the crosstalk delay, so that a delay fault, i f it exists, is detected. In this paper we present a new Au-Test Pattern Generation (ATPG)algorithm which maximizes the influence of crosstalk by appropriately activating the aggressors coupled to the victim nodes lying along any critical path.

Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. In order to avoid excessive conservatism in static timing analysis, it is important to determine if aggressor lines can potentially switch simultaneously with the victim. In this paper, we present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. We present results on several benchmark circuits that show the value of considering functional information to reduce the conservatism associated with worst-case coupled line switching assumptions during static timing analysis.